Apparatus and method for interfacing to a memory
View Patent ↗A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
1. A memory interface circuit, comprising:
a clock phase circuit for receiving a reference clock signal and for providing first, second, third and fourth corresponding clock phases each being shifted in phase relative to each other;
a first single to double data rate converting circuit for receiving a first type of data at a single data rate, the first corresponding clock phase and the third corresponding clock phase, the first type of data including a first data stream and a second data stream received synchronous to the first corresponding clock phase, the first single to double data rate converting circuit providing the first type of data at a double data rate corresponding to a combination of the first and the third corresponding clock phases and providing data of the first data stream and the second data stream synchronous to active edges of the first and the third corresponding clock phases; and
a second single to double data rate converting circuit for receiving a second type of data at the single data rate, the second corresponding clock phase and the fourth corresponding clock phase, the second single to double data rate converting circuit providing the second type of data at the double data rate corresponding to a combination of the second and the fourth corresponding clock phases.
2. The memory interface circuit of claim 1 , wherein the first, second, third and fourth corresponding clock phases are shifted in phase by multiples of 90 degrees relative to each other.
3. The memory interface circuit of claim 2 , wherein the second corresponding clock phase is shifted 90 degrees from the first corresponding clock phase, the third corresponding clock phase is shifted 180 degrees from the first corresponding clock phase, and the fourth corresponding clock phase is shifted 270 degrees from the first corresponding clock phase.
4. The memory interface circuit of claim 1 , wherein the first type of data includes one of write data, command data and address data.
5. The memory interface circuit of claim 1 , wherein the second type of data includes preset logic state data.
6. The memory interface of claim 1 , wherein the first single to double data rate converting circuit includes:
edge detection circuitry for detecting the active edges of the first and the third corresponding clock phases, and for providing a selection signal in response to each detected active edge;
a selection circuit for passing one bit of the first data stream in response to one state of the selection signal, and for passing one bit of the second data stream in response to another state of the selection signal; and
a register circuit for receiving and providing the one bit of the first data stream and the one bit of the second data stream synchronously with the detected active edges of the first and the third corresponding clock phases.
7. The memory interface circuit of claim 1 , wherein the second type of data includes a preset high logic state signal and a preset low logic state signal, the second single to double data rate converting circuit providing the high logic state signal and the low logic state signal synchronous to active edges of the second and the fourth corresponding clock phases.
8. The memory interface of claim 7 , wherein the second single to double data rate converting circuit includes:
edge detection circuitry for detecting the active edges of the second and the fourth corresponding clock phases, and for providing a selection signal in response to each detected active edge;
a selection circuit for passing the preset high logic state signal in response to one state of the selection signal, and for passing the preset low logic state signal in response to another state of the selection signal; and
a register circuit for receiving and providing the preset high logic state signal and the preset low logic state signal synchronously with the detected active edges of the second and the fourth corresponding clock phases.
9. The memory interface circuit of claim 1 , further including:
a clock delay circuit for receiving an output clock signal and a complementary output clock signal, the clock delay circuit providing a delayed output clock signal and a delayed complementary output clock signal; and
a data rate conversion circuit for receiving incoming data at the double data rate, the delayed output clock signal and the delayed complementary output clock signal, the data rate conversion circuit converting the incoming data to single data rate data in response to the delayed output clock signal and the delayed complementary output clock signal.
10. The memory interface of claim 9 , wherein the clock delay circuit includes a delay locked loop for delaying the delayed output clock signal by a phase shift of 90 degrees relative to the output clock signal, and for delaying the delayed complementary output clock signal by a phase shift of 90 degrees relative to the complementary output clock signal.
11. The memory interface of claim 9 , wherein the data rate conversion circuit includes:
a double to single data rate converting circuit for converting the incoming data into a first data stream and a second data stream, the first data stream and the second data stream being synchronized to the delayed output clock signal and the delayed complementary output clock signal, and
a clock domain conversion circuit for receiving the first data stream and the second data stream, and for synchronizing the first data stream and the second data stream to a control clock corresponding to the single data rate, the single data rate data corresponding to the first data stream and the second data stream synchronized to the control clock.
12. The memory interface of claim 11 , wherein the double to single data rate converting circuit includes
a first input register for latching a first bit of the incoming data in response to an active edge of the delayed output clock signal, and for providing a first buffered bit corresponding to the first data stream,
a second input register for latching a second bit of the incoming data in response to an active edge of the delayed complementary output clock signal, and for providing a second latched bit, and
a third input register for latching the second latched bit in response to the active edge of the delayed output clock signal, and for providing a second buffered bit, the second buffered bit corresponding to the second data stream.
13. The memory interface of claim 11 , wherein the clock domain conversion circuit includes a first-in first-out (FIFO) circuit having
input registers for receiving the first data stream and the second data stream, a write pointer for selectively enabling one input register in response to the delayed output clock signal,
a multiplexer for selectively passing outputs of the input registers in response to a selection signal, and
a read pointer circuit for providing the selection signal synchronized to the control clock, in response to a signal derived from the write pointer circuit.
14. A method for interfacing data between a memory and a system, comprising:
providing a plurality of clock phases from a reference clock;
converting system data to memory data in response to a combination of a first set of the plurality of clock phases, the memory data including memory address data, memory command data and memory write data, the memory command data including a memory read command for instructing the memory to output memory read data from an address corresponding to the memory address data;
providing a memory clock in response to a combination of a second set of the plurality of clock phases;
receiving echo clocks from the memory;
delaying the echo clocks to provide delayed echo clocks; and
converting the memory read data into system read data in response to the delayed echo clocks.
15. The method of claim 14 , wherein the memory command data can include a memory write command for instructing the memory to store the memory write data at an address corresponding to the memory address data.
16. The method of claim 14 , wherein the echo clocks are delayed by a 90 degree phase shift.
17. An apparatus for interfacing to a memory, comprising:
a clock phase providing circuit for receiving an input clock signal and for providing a plurality of corresponding clock phases;
a single to double data rate converting circuit for receiving data and at least two of the plurality of corresponding clock phases and for providing rate converted data at a rate corresponding to a combination of the at least two of the plurality of corresponding clock phases;
a clock delay circuit for receiving at least two clock signals related to incoming data and for delaying the clock signals; and
a data rate conversion circuit for receiving the incoming data and the delayed clock signals and for providing rate converted data at a rate corresponding to a combination of the delayed clocks.