Method and apparatus for synchronization of row and column access operations
View Patent ↗A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.
1. A semiconductor memory device comprising:
a plurality of memory cells,
a plurality of bitlines and word lines coupled to the plurality of memory cells;
a plurality of sense amplifiers for sensing and amplifying signals from the bit lines;
a plurality of column access devices for coupling the bit lines to a data line;
delay circuitry for providing a delayed word line timing pulse and a further delayed word line timing pulse in response to a word line timing pulse, the further delayed word line timing pulse being provided in response to the delayed word line timing pulse; and
enable circuitry for enabling the sense amplifier in response to the delayed word line timing pulse and for enabling the column access devices in response to the further delayed word line timing pulse.
2. The semiconductor memory device of claim 1 , wherein the delay circuitry comprising:
first delay circuitry for delaying the word line timing pulse to provide the delayed word line timing pulse; and
second delay circuitry for delaying the delayed word line timing pulse to provide the further delayed word line timing pulse.
3. The semiconductor memory device of claim 2 , wherein the enable circuitry is configured to enable the sense amplifier at a time corresponding to the delayed word line timing pulse and to enable the column access device at a time corresponding to the further delayed word line timing pulse.
4. An apparatus for operating a semiconductor memory device having a plurality of memory cells, a plurality of bit and word lines, the apparatus comprising:
a plurality of sense amplifiers for sensing and amplifying signals from the bit lines;
a plurality of column access devices for coupling the bit lines to a data line;
delay circuitry for providing a delayed word line timing pulse and a further delayed word line timing pulse in response to a word line timing pulse, the further delayed word line timing pulse being provided in response to the delayed word line timing pulse; and
enable circuitry for enabling the sense amplifier in response to the delayed word line timing pulse and for enabliny the column access device in response to the further delayed word line timing pulse.
5. The apparatus of claim 4 , wherein the delay circuitry of the semiconductor memory device comprises:
first delay circuitry for delaying the word line timing pulse to provide the delayed word line timing pulse; and
second delay circuitry for delaying the delayed word line timing pulse to provide the further delayed word line timing pulse.
6. The apparatus of claim 4 , wherein the enable circuitry of the semiconductor memory device is configured to enable the sense amplifier at a time corresponding to the delayed word line timing pulse and to enable the column access device at a time corresponding the further delayed word line timing pulse.
7. A method for operating a semiconductor memory device having a plurality of memory cells, a plurality of bit and word lines, the method comprising:
providing a delayed word line timing pulse in response to a word line timing pulse;
providing a further delayed word line timing pulse in response to the delayed word line timing pulse;
enabling the sense amplifier for sensing and amplifying signals from the bit lines in response to the delayed word line timing pulse; and,
enabling the column access device for coupling the bit lines to a data line of the memory device in response to the further delayed word line timing pulses.
8. The method of claim 7 , wherein the step of providing comprises:
delaying a word line timing pulse to provide the delayed word line timing pulse; and
delaying the delayed word line timing pulse to provide the further delayed word line timing pulse.
9. The method of claim 8 , wherein the step of enabling comprises:
enabling the sense amplifier at a time corresponding to the delayed word line timing pulse and
enabling the column access device at a time corresponding to the further delayed word line timing pulse.
10. The method of claim 8 , wherein the step of enabling comprises:
activating the sense amplifier in synchronization with the delayed word line timing pulse and
activating the column access device in synchronization with the further delayed word line timing pulse.