Port packet queuing
View Patent ↗A port queue includes a first memory portion having a first memory access time and a second memory portion having a second memory access time. The first memory portion includes a cache row. The cache row includes a plurality of queue entries. A packet pointer is enqueued in the port queue by writing the packet pointer in a queue entry in the cache row in the first memory. The cache row is transferred to a packet vector in the second memory. A packet pointer is dequeued from the port queue by reading a queue entry from the packet vector stored in the second memory.
1. A method of processing data packets in a switch comprising the steps of:
receiving data packets on an ingress port of the switch and writing the data packets to buffer memory of the switch;
writing in a first memory of an egress port of the switch, a plurality of pointers pointing to the data packets in the buffer memory, the first memory having a first memory access time;
establishing a linked list by transferring, in a single transfer cycle, the plurality of pointers to a second memory of the egress port, the second memory having a second memory access time that is significantly slower than the first memory access time; and
dequeuing each pointer from the second memory and forwarding the corresponding data packet from the egress port.
2. A queuing method as claimed in claim 1 wherein the step of writing writes each pointer in a single write operation to the first memory.
3. A queuing method as claimed in claim 1 wherein the step of transferring forwards a full cache row into the second memory.
4. A queuing method as claimed in claim 3 wherein the cache row is transferred in a single write cycle.
5. A queuing method as claimed in claim 1 wherein the step of transferring forwards a partially filled cache row into the second memory.
6. A queuing method as claimed in claim 5 wherein the cache row is transferred in single write cycle.
7. A queuing method as claimed in claim 1 wherein entries in a cache row in first memory are ordered by position in the cache row.
8. A queuing method as claimed in claim 1 wherein the first memory includes two cache rows.
9. A queuing method as claimed in claim 1 wherein a packet vector stored in the second memory includes a cache row and a count of the number of pointers stored in the cache row.
10. A queuing method as claimed in claim 9 wherein a packet vector stored in the second memory includes a link to a next packet vector.
11. A queuing method as claimed in claim 1 wherein a packet vector stored in the second memory includes a link to a next packet vector.
12. A queuing method as claimed in claim 1 wherein the plurality of pointers are packet pointers.
13. A queuing method as claimed in claim 1 wherein at least one of the plurality of pointers is written into an egress port queue.
14. A queuing method as claimed in claim 1 wherein each pointer is determined from a packet header of a data packet.