Circuit for clamping current in a charge pump
View Patent ↗A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
1. A method for clamping current in a charge pump, the charge pump including switching circuitry and a capacitor, and the charge pump defining first and second paths through which current is transmitted to/received from the capacitor, at least one parasitic spike in current from at least one of a number of transistors of the switching circuitry being generated during switching off of the at least one of the transistors, the at least one parasitic spike dissipated after elapse of a short period of time, the method comprising the steps of:
providing at least one control signal that causes the switching off of the at least one of the transistors when said at least one control signal changes from a first value to a second value;
switching a first transistor on to open an additional path for the current from the at least one of the transistors when said at least one control signal changes from said first value to said second value in order that the at least one parasitic spike is only partially communicated through a selected one of the first and second paths; and
switching a second transistor off to close said additional path after said additional path has been open for the short period of time.
2. The method as claimed in claim 1 , wherein the step of closing said additional path is carried out after the switching off of the at least one of the transistors.
3. The method as claimed in claim 1 , wherein the at least one parasitic spike is two parasitic spikes, each being generated in a different one of the
transistors of the switching circuitry, and one of the parasitic spikes being asymmetrical as compared to the other parasitic spike.
4. The method as claimed in claim 1 , wherein the transistors of the switching circuitry are FETs.
5. The method as claimed in claim 1 , wherein said first and second transistors are connected in series.
6. Apparatus comprising:
a charge pump including a number of switching transistors, a current clamping circuit and a capacitor, said charge pump defining first and second paths through which current is transmitted to/received from said capacitor, and one of said switching transistors located on a selected one of said first and second paths, the switching transistor generating a parasitic spike in current when it switches off, said parasitic spike dissipated after elapse of a short period of time; and
an input providing a control signal for causing the switching off of the switching transistor when said control signal changes from a first value to a second value,
said current clamping circuit for (i) switching a first transistor on to open an additional path for the current from the switching transistor when the control signal changes from said first value to said second value in order that said parasitic spike is only partially communicated through the one of the first and second paths; and (ii) switching a second transistor off to close said additional path after said additional path has been open for said short period of time.
7. The apparatus as claimed in claim 6 , wherein said charge pump further includes first and second FETs both electrically connected to said capacitor, said first FET positioned along said first path, said second FET positioned along said second path.
8. The apparatus as claimed in claim 6 , wherein said current clamping circuit includes two similar transistors connected in series and located along said additional path, a drain of one of said similar transistors located on said first node.
9. The apparatus as claimed in claim 8 , wherein said current clamping circuit further includes delay introducing circuitry having an input and an output, said output electrically connected to a gate of the other of said similar transistors, the delay introduced by said delay introducing circuitry equal in duration to said short period of time.
10. The apparatus as claimed in claim 6 , wherein said charge pump is comprised of bipolar transistors.
11. The apparatus as claimed in claim 6 , wherein said first and second transistors are connected in series.