Scalable memory system
View Patent ↗A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
1. A memory system comprising:
a controller having a serial channel output port for providing a serial bitstream command packet, a control output port for providing a data output control signal, and a serial channel input port for receiving a serial bitstream read data packet, the serial bitstream command packet including an operational code and a device address;
a memory device having an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device, and a control input port for receiving the data output control signal, the memory device providing the serial bitstream command packet through an output port and subsequently providing the serial bitstream read data packet through the output port in response to the data output control signal if the operation code corresponds to a read function; and
an expansion link between the controller and the memory device, to which one of a memory expansion module and a jumper is insertable.
2. The memory system of claim 1 , further including at least one intervening memory device coupled in series between the memory device and the controller, the at least one intervening memory device having an input port for receiving and passing the serial bitstream command packet to the memory device, and subsequently providing the serial bitstream read data packet if the device address corresponds to the memory device and the operation code corresponds to a read function.
3. The memory system of claim 2 , wherein complementary clock signals are provided to the memory device and the at least one intervening memory device in parallel.
4. The memory system of claim 2 , wherein complementary clock signals are provided to the at least one intervening memory device, and passed by the at least one intervening memory device to the memory device, and passed by the memory device to the controller.
5. The memory system of claim 2 , wherein the at least one intervening memory device is part of the memory expansion module having coupling means configured for electrical coupling with the expansion link.
6. The memory system of claim 2 , wherein the memory device and the at least one intervening memory device each include a native memory core and a serial interface and control logic block for controlling the native memory core in response to the serial bitstream command packet.
7. The memory system of claim 6 , wherein the memory device native memory core and the at least one intervening memory device native memory core are NAND flash based.
8. The memory system of claim 6 , wherein the memory device native memory core and the at least one intervening memory device native memory core are different.
9. The memory system of claim 2 , wherein the native memory core includes one of DRAM, SRAM, NAND flash and NOR flash memory cores.
10. The memory system of claim 1 , wherein the serial bitstream command packet has a modular structure where the size of the serial bitstream command packet is variable.
11. The memory system of claim 10 , wherein the serial bitstream command packet includes a command field for providing the operation code and the device address.
12. The memory system of claim 11 , wherein the command field includes a first sub-field for providing the operation code, and a second sub-field for providing the device address.
13. The memory system of claim 10 , wherein the serial bitstream command packet includes a command field for providing the operation code and the device address, and an address field for providing one of a row address and a column address.
14. The memory system of claim 10 , wherein the serial bitstream command packet includes a command field for providing the operation code and the device address, an address field for providing one of a row address and a column address, and a data field for providing write data.
15. The memory system of claim 10 , wherein the controller provides a command strobe in parallel with the serial bitstream command packet, the command strobe having an active level matching the length of the serial bitstream command packet.
16. The memory system of claim 15 , wherein the controller provides a data input strobe in parallel with the serial bitstream read data packet, the data input strobe having an active level matching the length of the serial bitstream read data packet.
17. The memory system of claim 16 , wherein the memory device latches the serial bitstream command packet in response to the active level of the command strobe when the device address corresponds to the memory device.
18. The memory system of claim 17 , wherein the memory device input port is enabled in response to the active level of the data input strobe.
19. The memory system of claim 18 , wherein the command strobe and the data input strobe are non-overlapping signals.
20. The memory system of claim 18 , wherein the command strobe and the data input strobe are separated by at least one data latching clock edge.
21. The memory system of claim 18 , wherein the command strobe is separated from an adjacent command strobe by at least one data latching clock edge.
22. The memory system of claim 18 , wherein the data input strobe is separated from an adjacent data input strobe by at least one data latching clock edge.
23. The memory system of claim 1 , wherein the memory expansion module receives the serial bitstream command packet and passes the serial bitstream command packet to one of the memory device or the controller.
24. The memory system of claim 23 , wherein the memory expansion module includes at least one intervening memory device for receiving the serial bitstream command packet and outputting the serial bitstream command packet.
25. The memory system of claim 1 , wherein the jumper and the memory expansion module are releasably retained in the at least one expansion link.
26. The memory system of claim 25 , wherein the jumper is inserted into the at least one expansion link in a first configuration of the memory system, and the memory expansion module is inserted into the at least one expansion link in a second configuration of the memory system having a memory capacity greater than the first configuration.
27. The memory system of claim 25 , wherein the at least one expansion link includes a first terminal for receiving the serial bitstream command packet and a second terminal for providing the serial bitstream command packet, the jumper being configured for electrically coupling the first terminal to the second terminal when inserted into the at least one expansion link.
28. The memory system of claim 1 , wherein the at least one expansion link includes at least two expansion links serially connected between the controller and the memory device.
29. A memory system comprising:
a plurality of memory devices;
a controller for controlling the devices,
wherein the controller has an output port for providing a bitstream command packet to a first device of the plurality of memory devices and a control output port for providing a data output control signal, the bitstream command packet including an operational code and a device address,
each of the plurality of memory devices receiving the bitstream command packet and the data output control signal from one of the controller and a prior memory device and executing the operation code if the device address corresponds thereto, each of the plurality of memory devices providing the bitstream command packet to one of a next memory device and the controller, a bitstream read data packet being provided from a last memory device of the plurality of memory devices to the controller in response to the data output control signal if the operation code corresponds to a read function; and
at least one expansion link coupled between
the controller and a memory device of the plurality of memory devices, or
between two adjacent memory devices of the plurality of memory devices, the expansion link configured for insertion of one of a memory expansion module and a jumper.
30. The memory system of claim 29 , wherein the plurality of memory devices is connected in series, the first and last memory devices being connected to the controller.
31. The memory system of claim 29 , wherein the controller sends a bitstream data packet to the first device of the plurality of memory devices.
32. The memory system of claim 31 , wherein the bitstream data packet from the controller and the bitstream read data packet comprises a serial bitstream.
33. The memory system of claim 31 , wherein the bitstream data packet from the controller and the bitstream read data packet comprises parallel bitstreams.
34. The memory system of claim 29 , wherein the plurality of memory devices are of the same type or a mix of different types of memory devices.
35. The memory system of claim 29 , wherein the memory expansion module receives the bitstream command packet and passes the bitstream command packet to one of the plurality of memory devices or the controller.
36. The memory system of claim 35 , wherein the memory expansion module includes at least one intervening memory device for receiving the bitstream command packet and outputting the bitstream command packet.
37. The memory system of claim 29 , wherein the jumper and the memory expansion module are releasably retained in the at least one expansion link.
38. The memory system of claim 37 , wherein the jumper is inserted into the at least one expansion link in a first configuration of the memory system, and the memory expansion module is inserted into the at least one expansion link in a second configuration of the memory system having a memory capacity greater than the first configuration.
39. The memory system of claim 37 , wherein the at least one expansion link includes a first terminal for receiving the bitstream command packet and a second terminal for providing the bitstream command packet, the jumper being configured for electrically coupling the first terminal to the second terminal when inserted into the at least one expansion link.
40. The memory system of claim 29 , wherein the at least one expansion link includes
at least two expansion links serially connected between the controller and the memory device, or
between the two adjacent memory devices.