Asynchronous ID generation
View Patent ↗A technique for automatically establishing device IDs for devices in a daisy chain cascade arrangement. For each device, a write ID operation is initiated at the device to cause the device to enter a generate/write ID mode. While in this mode, a first value is input to the device. The device generates a second value from the first value. The device outputs the generated second value from the device to a next device in the daisy chain cascade which uses the second value as a first value for the next device. The device then establishes its ID from the first value. The process is repeated for all devices in the daisy chain cascade arrangement.
1. A method of assigning an identifier (ID) for a memory device configured in a daisy chain cascade arrangement having a plurality of devices, the method comprising:
processing, at a first memory device in the daisy chain cascade arrangement, a command causing the first device to enter a mode for assigning an identifier;
asynchronously asserting an input to input a first value to the first memory device independent of a clock signal;
asynchronously producing a second value from the first value independent of a clock signal;
asynchronously asserting an output to output the second value from the first memory device to a second memory device in the daisy chain cascade arrangement independent of a clock signal, the output being configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and
holding an ID established for the first memory device based on the first value.
2. A method as defined in claim 1 wherein inputting a first value to a first memory device includes acquiring a state of input of the first device.
3. A method as defined in claim 1 wherein holding an ID for the first memory device includes placing the first value in storage associated with the first memory device.
4. A method as defined in claim 3 wherein the storage is a device ID register for the first memory device.
5. A method as defined in claim 1 wherein producing the second value includes:
adding a predetermined value to the first value to generate the second value.
6. A memory device configured in a daisy chain cascade arrangement having a plurality of memory devices, the memory device comprising:
control circuitry configured to process a command causing the device to enter a mode for assigning an identifier;
input circuitry configured to input, asynchronously and independent of a clock signal, a first value into the memory device;
output circuitry configured to output, asynchronously and independent of a clock signal, a second value generated asynchronously and independent of a clock signal from the first value to a second memory device in the daisy chain cascade via one or more outputs of the device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and
holding circuitry configured to hold an identifier established (ID) for the memory device based on the first value.
7. A memory device as defined in claim 6 wherein the input circuitry further comprises circuitry configured to acquire a state of input of the first memory device.
8. A memory device as defined in claim 6 wherein the holding circuitry comprises storage associated with the memory device, the storage configured to store the established ID for the device.
9. A memory device as defined in claim 6 further comprising:
adder circuitry configured to add a third value to the first value to generate the second value.
10. A device as defined in claim 9 wherein the third value is a predetermined value.
11. A device as defined in claim 6 wherein the output circuitry includes:
one or more output buffers configured to output the value to the second memory device in the daisy chain cascade.
12. A daisy chain cascade arrangement having a plurality of devices, the arrangement comprising:
a first memory device comprising:
control circuitry configured to process a command causing the first memory device to enter a mode for assigning an identifier;
input circuitry configured to input, asynchronously and independent of a clock signal, a first value into the first memory device;
producing circuitry configured to produce, asynchronously and independent of a clock signal, a second value from the first value;
output circuitry configured to output, asynchronously and independent of a clock signal, the second value to a second memory device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and
holding circuitry configured to hold a first identifier (ID) established for the first memory device, the first ID based on the first value; and
a second memory device comprising:
control circuitry configured to process a command causing the second memory device to enter a mode for assigning an identifier;
input circuitry configured to input the second value into the second memory device;
producing circuitry configured to produce a third value from the second value;
output circuitry configured to output the third value to a third memory device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and
holding circuitry configured to hold a second identifier (ID) established for the second memory device, the second ID based on the second value.
13. A daisy chain cascade arrangement as defined in claim 12 wherein:
the input circuitry of the first device comprises circuitry for acquiring the state of input of the first memory device; and
the input circuitry of the second device comprises circuitry for acquiring the state of input of the second memory device.
14. A daisy chain cascade arrangement as defined in claim 12 wherein:
the holding circuitry of the first memory device comprises establishing circuitry for placing the first ID in storage associated with the first memory device; and
the holding circuitry of the second memory device comprises establishing circuitry for placing the first ID in storage associated with the second memory device.
15. A daisy chain cascade arrangement as defined in claim 12 wherein each of the first and second memory devices establishes the ID in response to an ID entry.
16. A daisy chain cascade arrangement as defined in claim 12 wherein:
the producing circuitry of the first memory device comprises circuitry for adding a predetermined value to the first value to produce the second value.