Granted Patent B2

US 6,873,568 · App. 10/337,972 · Granted Mar 29, 2005

Abstract

Claims (35)

1. A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering said sense amplifiers, said circuit comprising:

(a) a first delay circuit for delaying a word line timing pulse by a first predetermined period;

(b) a first logic circuit for logically combining said word line timing pulse and said delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit;

(c) a second delay circuit for delaying said word line timing pulse by a second predetermined period; and

(d) a second logic circuit for logically combining said word line timing pulse and said second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein said second predetermined time period is selected so that ones of a plurality of column access devices are activated after said sense amplifier power supply circuit is enabled.

2. A circuit as defined in claim 1 , wherein said first delay circuit is a first delay element.

3. A circuit as defined in claim 1 , wherein said second delay circuit is a second delay element.

4. A circuit as defined in claim 3 , wherein said second delay element is coupled with said word line timing pulse via said first delay element.

5. A circuit as defined in claim 4 , wherein said circuit further comprises a plurality of logic circuits for logically combining said column select enable signal with a plurality of column address signals for enabling said selected ones of a plurality of column access devices.

6. A circuit as defined in claim 3 , wherein said second predetermined time is longer than said first predetermined time.

7. A circuit as defined in claim 6 , wherein said circuit further comprises a third delay element for delaying said word line timing pulse before said word line timing pulse is input to said first logic circuit.

8. A circuit as defined in claim 6 , wherein said circuit further comprises a third delay element for delaying said word line timing pulse before said word line timing pulse is input to said second logic circuit.

9. A circuit as defined in claim 2 , wherein said second delay circuit is a comparator having a first input coupled to a power signal of said sense amplifier power supply circuit and a second input coupled to a predetermined threshold voltage, said comparator having an output that is asserted depending on a comparison between said first and second inputs.

10. A circuit as defined in claim 9 , wherein said first input is coupled to a p-channel power signal of said sense amplifier power supply circuit and said output of said comparator is asserted if said p-channel power signal is greater than said threshold.

11. A circuit as defined in claim 10 , wherein a third delay circuit is coupled between said output of said comparator and said second logic circuit.

12. A circuit as defined in claim 9 , wherein said first input is coupled to an n-channel power signal of said sense amplifier power supply circuit and said output of said comparator is asserted if said n-channel power signal is less than said threshold.

13. A circuit as defined in claim 12 , wherein a third delay circuit is coupled between said output of said comparator and said second logic circuit.

14. A method for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering said sense amplifiers, said method comprising the steps of:

(a) generating a word line timing pulse for activating of at least one of said word lines;

(b) delaying said word line timing pulse by a first predetermined time;

(c) logically combining said word line timing pulse and said first delayed word line timing pulse for providing a sense amplifier enable signal, said sense enable signal for enabling said sense amplifier power supply circuit;

(d) delaying said word line timing pulse by a second predetermined time; and

(e) logically combining said word line timing pulse and said second delayed word line timing pulse for providing a column select enable signal, said column select enable signal for enabling selected ones of a plurality of column access devices wherein said selected ones of a plurality of column access devices are activated a predetermined time period after said sense amplifier power supply circuit is enabled.

15. A method as defined in claim 14 , wherein said column select enable signal is logically combined with a plurality of column address signals for enabling said selected ones of a plurality of column access devices.

16. A method as defined in claim 14 , wherein said second predetermined time is longer than said first predetermined time.

17. A method as defined in claim 14 , wherein said word line timing pulse is delayed before being logically combined with said first delayed world line timing pulse.

18. A method as defined in claim 14 , wherein said word line timing pulse is delayed before being logically combined with said second delayed world line timing pulse.

19. A method as defined in claim 14 , wherein said word line timing pulse is delayed by a first predetermined time by coupling said word line timing pulse with a first delay circuit.

20. A method as defined in claim 19 , wherein said word line timing pulse is delayed by a second predetermined time by coupling said word line timing pulse with a second delay circuit.

21. A method as defined in claim 20 , wherein said word line timing pulse is delayed by a second predetermined time by coupling said word line timing pulse with both said first and said second delay circuits.

22. A method as defined in claim 21 , wherein said second delay circuit is a comparator having a first input coupled to a power signal of said sense amplifier power supply circuit and a second input coupled to a predetermined threshold voltage, said comparator having an output that is asserted depending on a comparison between said first and second inputs.

23. A method as defined in claim 22 , wherein said first input of said comparator is coupled to a p-channel power signal of said sense amplifier power supply circuit and said output of said comparator is asserted if said p-channel power signal is greater than said threshold.

24. A method as defined in claim 23 , wherein a third delay circuit is coupled between said output of said comparator and said second logic circuit.

25. A method as defined in claim 22 , wherein said first input of said comparator is coupled to an n-channel power signal of said sense amplifier power supply circuit and said output of said comparator is asserted if said n-channel power signal is less than said threshold.

26. A method as defined in claim 25 , wherein a third delay circuit is coupled between said output of said comparator and said second logic circuit.

Assignments (9)