Dynamic random access memory with fully independent partial array refresh function
View Patent ↗A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
1. A dynamic random access memory (DRAM) device comprising:
a memory having M memory subblocks, M being an integer greater than one, each subblock having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshed by refresh operation; and
a refresh circuit for controlling in a refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set;
wherein the refresh circuit comprises:
a configuration circuit for configuring the M subblock refresh data in response to input data, the M subblock refresh data being independently set by the input data;
wherein the configuration circuit comprises:
a latch circuit for holding the input data, the M subblock refresh data being produced in accordance with the held input data.
2. The DRAM device of claim 1 , wherein the latch circuit comprises:
M latching circuits for latching the M subblock refresh data, each of the M latching circuit latching the respective one of the M subblock refresh data independently.
3. The DRAM device of claim 2 , further comprising:
a first address producing circuit for producing N first addresses in the refresh mode, N being an integer.
4. The DRAM device of claim 3 , wherein the refresh circuit further comprises:
a subblock address controlling circuit for controlling the refreshing of the memory subblocks in response to the logical combination of the N first addresses and the M subblock refresh data.
5. The DRAIVI device of claim 4 , wherein the subblock address controlling circuit comprises:
a first address decoding circuit including
M decoding circuits for decoding the first addresses to produce M decoded first address outputs, and
M logic circuits for logically combining the M decoded first address outputs and the M subblock refresh data, thereby producing M first addresses.
6. The DRAM device of claim 5 , further comprising:
a second address producing circuit for producing addresses, the second address producing circuit including M decoding circuits for decoding the second addresses to produce M decoded second addresses.
7. The DRAIVI device of claim 6 , wherein the first address decoding circuit further includes:
a subblock selection circuit having
M selecting circuits for selecting the M decoded first addresses in the refresh mode or the M decoded second addresses in the non-refresh mode, the M selected addresses designating the memory subblock to be refreshed.
8. The DRAM device of claim 7 , wherein:
the first address producing circuit comprises an internal address producer for producing internal addresses as the first addresses; and
the second address producing circuit comprises an external address producer for producing external addresses as the second addresses.
9. The DRAM device of claim 8 , further comprising:
a command controlling circuit for controlling the latching of the input data by the configuration circuit and for detecting the refresh mode, the producing of the address by the address producing circuit and the selection by the subblock selection circuit being controlled in response to the detection of the refresh mode.
10. The DRAM device of claim 9 , wherein the command controlling circuit comprises:
a mode detection circuit for detecting a self-refresh mode in the DRAM device.
11. The DRAM device of claim 2 , further comprising:
a first address producing circuit for producing first addresses in the refresh mode; and
a second address producing circuit for producing external addresses.
12. The DRAM device of claim 11 , wherein the refresh circuit comprises:
a subblock address controlling circuit for controlling the refreshing of the memory subblocks in response to the logical combination of the first addresses, the second addresses and the M subblock refresh data.
13. The DRAM device of claim 12 , wherein the subblock address controlling circuit comprises:
a selecting circuit for selecting the first addresses in the refresh mode or the second addresses in the non-refresh mode to produce selected addresses.
14. The DRAM device of claim 13 , wherein the subblock address controlling circuit further comprises:
an address decoding circuit for decoding the selected addresses to produce M decoded addresses.
15. The DRAM device of claim 14 , wherein the subblock address controlling circuit further comprises:
a subblock selecting circuit for logically combining the M decoded addresses and the M subblock refresh data to produce M selected addresses designating the memory subblock to be refreshed.
16. The DRAM device of claim 15 , wherein:
the selecting circuit comprises N selectors for selecting the N first addresses or the N second addresses to produce N selected addresses;
the address decoding circuit comprises M logic circuits for decoding the N selected addresses to produce M decoded addresses; and
the subblock selecting circuit comprises M logic circuits for logically combing the M decoded addresses and the M subblock refresh data to produce the M selected addresses.
17. The DRAM device of claim 16 , wherein:
the first address producing circuit comprises an internal address producer for producing internal addresses as the first addresses; and
the second address producing circuit comprises an external address producer for producing external addresses as the second addresses.
18. The DRAM device of claim 17 , further comprising:
a command controlling circuit for controlling the latching of the input data by the configuration circuit and for detecting the refresh mode, the producing of the address by the address producing circuit and the selection by the selecting circuit being controlled in response to the detection of the refresh mode.
19. A method for refreshing a dynamic random access memory device including M memory subblocks, M being an integer greater than one, each subblock having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshed in a refresh mode, the method comprising:
controlling in a refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set;
wherein the step of controlling comprising:
configuring the M subblock refresh data in response to input data, the M subblock refresh data being independently set by the input data;
wherein the step of configuring comprising:
holding the input data, the M subblock refresh data being produced in accordance with the held input data.
20. The method of claim 19 , further comprising:
providing an address signal for selecting the subblock.
21. The method of claim 20 , further comprising:
latching the M subblock refresh data, each data being latched independently.
22. The method of claim 21 , further comprising:
providing an address signal for selecting the subblock.
23. The method of claim 22 , further comprising:
producing an address in a refresh mode; and
decoding the address to produce M addresses which are logically combined with the M subblock refresh data, so that M decoded addresses are provided for selecting the M subblocks.
24. A refresh controller for use in a dynamic random access memory device selectively operated in a refresh mode and a non self-refresh mode, the DRAM device including M memory subblocks, M being an integer greater that one, each subblock having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshed in a refresh mode, the refresh controller comprising:
a refresh circuit for controlling in refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set;
a configuration circuit for configuring the M subblock refresh data in response to input data, the M subblock refresh data being independently set by the input data;
wherein the configuration circuit comprising:
a latch circuit for holding the input data, the M subblock refresh data being produced in accordance with the held input data.