Source side asymmetrical precharge programming scheme
View Patent ↗A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.
1. A flash memory device comprising:
a driver for driving a source line select device, memory cells and a string select device connected in series between a bitline and a source line; and
a controller for controlling the driver in a programming operation, the controller being configured to
drive all wordlines of the memory cells to a first pass voltage for coupling a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage,
continue driving all the wordlines except a first wordline corresponding to a first memory cell adjacent to a selected memory cell to second pass voltage greater than the first pass voltage, the first memory cell being positioned between the selected memory cell and the string select device,
drive a second wordline corresponding to a second memory cell adjacent to the selected memory cell to a first supply voltage for turning off the second memory cell,
drive a third wordline corresponding to the selected memory cell to a programming voltage greater than the second pass voltage, and
couple the bitline to the selected memory cell.
2. The flash memory device of claim 1 , wherein the driver includes
wordline drivers for coupling row signals to the memory cells, a source select signal to the source line select device and a string select signal to a string select device,
a block decoder for enabling the wordline drivers in response to a block address, and,
a row decoder for providing the row signals, the source select signal and the string select signal in response to a row address.
3. The flash memory device of claim 2 , wherein the row decoder includes a row decoder circuit for providing one of the row signals, the row decoder circuit including a multiplexor for selectively coupling one of the programming voltage, the first pass voltage and the second pass voltage to the one of the row signals.
4. The flash memory device of claim 3 , wherein the row decoder includes a row decoder circuit for providing the source select signal, the row decoder circuit including a multiplexor for selectively coupling one of VSS and the second pass voltage to the source select signal.
5. The flash memory device of claim 3 , wherein the row decoder includes a row decoder circuit for providing the string select signal, the row decoder circuit including a multiplexor for selectively coupling one of VSS and VDD to the string select signal.