High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A Dynamic Random Access Memory (DRAM) for performing read, write, and refresh operations, said DRAM comprising:
(a) a plurality of sub-arrays, each comprising a plurality of memory cells, each memory cell is coupled to a bit line of a complementary bit line pair of a plurality of complementary bit line pairs, and to a word line of a plurality of word lines;
(b) a word line enable circuit for activating a selected one of said plurality of word lines;
(c) a column select circuit for activating a selected one of said plurality of bit line pairs;
(d) a timing circuit for controlling said word line enable circuit, said column select circuit, and said read, write, and refresh operations in response to a word line timing pulse; and
(e) wherein each sub-array of said plurality of sub-arrays comprise separate, dedicated plurality of bit line sense amplifiers.
2. The DRAM as claimed in claim 1 wherein a number of memory cells per bit line in each sub-array is substantially less than in conventional DRAM designed for the same process technology.
3. The DRAM as claimed in claim 2 wherein a number of memory cells per bit line in each sub-array is limited to 64.
4. The DRAM as claimed in claim 2 , wherein all word line activating and bit line activating signals have independent timing paths.
5. The DRAM as claimed in claim 1 , wherein all word line activating and bit line activating signals are generated locally within each said sub-array and triggered by the word line timing pulse.
6. The DRAM as claimed in claim 1 further comprising a logic gate associated with said each sub-array for combining the word line timing pulse with a delayed version thereof to provide a sense amplifier power supply enable signal.
7. The DRAM as claimed in claim 6 further comprising a delay element for delaying the word line timing pulse to provide the delayed version thereof.
8. The DRAM as claimed in claim 7 wherein the delay introduced by the delay element is precisely controlled.
9. The DRAM as claimed in claim 8 further comprising a second delay element for delaying the sense amplifier power supply enable signal to generate a column select enable signal.
10. The DRAM as claimed in claim 9 wherein the delay introduced by the delay element is precisely controlled.
11. The DRAM as claimed in claim 10 further comprising a second logic gate associated with each said sub-array for combining the column select enable signal with global column select address signals to provide a local column select signal.
12. The DRAM as claimed in claim 11 further comprising a column access circuit for receiving the local column select signal for each read, write or refresh operation.
13. The DRAM as claimed in claim 1 wherein read, write and refresh operations perform full row access and subsequent bit line and data line precharge and equalization, and tracking open banks is not required.