High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A method for accessing a dynamic random access memory (DRAM), the DRAM having a plurality of memory storage elements arranged in rows and columns, the method comprising steps of:
a) initiating a first memory access by providing a first address signal indicative of the location of at least one memory storage element to be accessed;
b) decoding the first address signal to select a row and at least one column corresponding to the location of the at least one memory storage element;
c) enabling a word line corresponding to the selected row;
d) activating a sense amplifier to latch data to or from the at least one selected column;
e) disabling the word line corresponding to the selected row;
f) precharging the at least one selected column;
g) initiating a second memory access by providing a second address signal indicative of the location of at least one memory storage element to be accessed; and
h) decoding the second address signal to select a row and at least one column corresponding to the location of the at least one memory storage element, the second memory access commencing before the step of precharging the selected column has completed.
2. A method according to claim 1 , wherein the step of decoding the second address signal occurs at substantially the same time as the precharging step.
3. A method according to claim 1 , wherein the memory storage elements are arranged in a plurality of sub-arrays and the method further comprises decoding the first and second address signals to select at least one sub-array.
4. A method according to claim 1 , wherein decoding the first address signal comprises decoding a row address and a column address at substantially the same time.
5. A method according to claim 1 , wherein decoding the second address signal comprises decoding a row address and a column address at substantially the same time.
6. A method according to claim 1 , wherein the memory access is one of a read access, a write access, or a refresh access.
7. A method according to claim 1 , including the step of deriving a plurality of self timed clock pulses from a system clock signal for controlling the timing of steps (b) to (f).
8. A method according to claim 1 , including the step of performing memory accesses on consecutive cycles of a system clock signal.
9. A dynamic random access memory (DRAM) comprising:
a) a plurality of memory storage elements arranged in rows and columns, each memory storage element being coupled to a bit pair line and a word line;
b) a row decoder for decoding row addresses from address signals received in respective clock periods and for asserting word line signals on word lines corresponding to the decoded row addresses;
c) a column decoder for decoding column addresses from the address signals and for selecting at least one corresponding bit line pair;
d) precharge circuitry for precharging the at least one pair of bit lines; and
e) timing circuitry for controlling activation of the precharge circuitry such that the precharging of memory storage elements selected by a first address signal occurs at substantially the same time as a next address signal is being decoded by the row and column decoders regardless of which memory storage elements are selected by the first and next address signals.
10. A DRAM according to claim 9 , wherein the memory storage elements are arranged in a plurality of sub-arrays, the DRAM further comprising a sub-array decoder for decoding the address signal to provide a sub-array select signal.
11. A DRAM according to claim 10 , wherein each sub-array comprises a data line, the data line capable of being coupled to the selected bit line.
12. A DRAM according to claim 9 , wherein the DRAM is an embedded DRAM.
13. A DRAM according to claim 9 , further comprising an address register for latching the address signal in response to a system clock signal.
14. A DRAM according to claim 9 , wherein the decoded row address is combined with a word line timing pulse to assert the word line signal on the word line.
15. A DRAM according to claim 9 , wherein the timing circuitry comprises a delay element that is used to provide a time delayed version of a system clock signal for synchronizing the activation of the precharge circuitry.
16. A DRAM according to claim 9 , wherein the address signal comprises N bits defining the column address and M bits defining the row address.
17. A DRAM according to claim 9 , wherein the row decoder and the column decoder decode the address signal at substantially the same time.