Timing vernier using a delay locked loop
View Patent ↗A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.
1. A method for synchronizing a plurality of delay elements with a reference timing signal, comprising:
providing a delay pulse having a duration adjustable in response to a bias voltage, wherein providing the delay pulse comprises:
generating a first pulse with a first delay in response to a delay signal,
generating a second pulse with a second delay in response to the delay signal, and
providing the delay pulse having the duration corresponding to a time between the first pulse and the second pulse;
adjusting the bias voltage in response to a time difference between a reference timing signal pulse duration and the duration of the delay pulse; and,
applying said bias voltage to the plurality of delay elements.
2. The method for synchronizing of claim 1 , wherein each of the delay elements corresponds to a delay segment of a timing vernier.
3. The method for synchronizing of claim 1 , wherein the step of providing comprises:
latching an active edge of the delay pulse in response to the first pulse, and resetting the delay pulse in response to the second pulse.
4. The method for synchronizing of claim 1 , wherein
the step of generating the first pulse comprises setting a first control timing by a first control timing circuit; and
the step of generating the second pulse comprises setting a second control timing by a second control timing circuit.
5. The method for synchronizing of claim 4 , wherein the first control timing circuit is set to provide the first pulse with a minimum delay, and the second control timing circuit is set to provide the second pulse with a maximum delay.
6. The method for synchronizing of claim 5 , wherein the first control circuit is set by providing a first set of programming bits and the second control circuit is set by providing a second set of programming bits.
7. The method for synchronizing of claim 5 , wherein the first control timing circuit and the second control timing circuit are control verniers.
8. The method for synchronizing of claim 7 , wherein a timing vernier includes the plurality of delay elements.
9. The method for synchronizing of claim 1 , wherein the step of adjusting comprises controlling a charge pump to adjust the bias voltage towards a first voltage for the reference timing signal pulse duration and for adjusting the bias voltage towards a second voltage for the duration of the delay pulse.
10. The method for synchronizing of claim 9 , wherein the step of controlling comprises:
charging by the charge pump the bias voltage towards the first voltage for the reference timing signal pulse duration; and
discharging by the charge pump the bias voltage towards the second voltage for the duration of the delay pulse.
11. The method for synchronizing of claim 1 , further comprising filtering the bias voltage before the step of applying.