Semiconductor memory asynchronous pipeline
View Patent ↗An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.
1. A synchronizing circuit for resynchronizing output data of an asynchronous pipeline with a clock and in accordance to a predetermined latency, the circuit comprising:
a latch enable signal generator responsive to the clock for sequentially generating and providing to a plurality of latches
a plurality of latch input enable signals, each having an asynchronous delay in relation to the clock for enabling one of the plurality of latches to latch a corresponding portion of the output data, the plurality of latch input enable signals corresponding to respective control signals, and
a plurality of latch output enable signals, each having a delay responsive to the predetermined latency for enabling a respective one of the plurality of latches to output the corresponding portion of the output data, the plurality of latch output enable signals corresponding to the respective control signals; and
an output buffer for receiving the corresponding portions of the output data from the plurality of latches and resynchronizing each of the corresponding portions of the output data with the clock.
2. The synchronizing circuit of claim 1 wherein the plurality of latches comprises a first-in-first-out (FIFO) register.
3. The synchronizing circuit of claim 1 wherein a number of the plurality of latches is substantially equal to the predetermined latency.
4. The synchronizing circuit of claim 1 wherein a number of the plurality of latches is substantially equal to double the predetermined latency.
5. The synchronizing circuit of claim 1 wherein the latch enable signal generator comprises a counter for counting a number of cycles of the clock and providing count signals, the respective control signals including the count signals.
6. The synchronizing circuit of claim 5 wherein the latch enable signal generator comprises:
a count delay circuit for delaying the count signals and providing delayed count signals; and
a count synchronization latch for receiving the delayed count signals and using the delayed count signals to provide the plurality of latch input enable signals.
7. The synchronizing circuit of claim 5 wherein the latch enable signal generator comprises a pipe delay circuit for receiving the count signals and using the count signals to provide the plurality of latch output enable signals.
8. The synchronizing circuit of claim 4 wherein the output buffer comprises means for resynchronizing the output data from the plurality of latches on a rising edge and a falling edge of the clock.
9. The synchronizing circuit of claim 1 further comprising a delay-locked-loop (DLL) for providing in response to the clock, a clock leading signal for clocking the output buffer.
10. The synchronizing circuit of claim 1 , wherein the control signals are generated by a ring counter.
11. A method for resynchronizing output data of an asynchronous pipeline with a clock and in accordance to a predetermined latency, the method comprising the steps of:
generating in response to the clock
a plurality of latch input enable signals, each having an asynchronous delay in relation to the clock, the plurality of latch input enable signals corresponding to respective control signals, and
a plurality of latch output enable signals, each having a delay responsive to the predetermined latency, the plurality of latch output enable signals corresponding to the respective control signals; and
latching corresponding portions of the output data in response to the plurality of latch input enable signals;
outputting the corresponding portions of the output data from the plurality of latches in response to the plurality of latch output enable signals; and
resynchronizing each of the corresponding portions of the output data with the clock.
12. The method of claim 11 wherein the step of generating in response to the clock a plurality of latch input enable signals comprises the steps of:
counting a number of cycles of the clock and providing count signals, the respective control signals including the count signals;
delaying the count signals and providing delayed count signals; and
synchronizing the delayed counts signal to provide the plurality of latch input enable signals.
13. The method of claim 11 wherein the step of generating in response to the clock a plurality of latch output enable signals comprises the steps of:
counting a number of cycles of the clock for providing count signals, the respective control signals including the count signals; and
delaying the count signals for providing the plurality of latch output enable signals.
14. The method of claim 13 wherein, in the step of delaying, the count signals are delayed in response to the predetermined latency.
15. The method of claim 11 wherein the step of resynchronizing includes:
providing in response to the clock, a clock leading signal from a delay-locked-loop (DLL); and
clocking the output buffer with the clock leading signal.
16. The method of claim 11 , wherein the step of generating is preceded by the step of using a counter for generating the control signals.