Low leakage and data retention circuitry
View Patent ↗An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
1. An integrated circuit comprising:
two power supply terminals for powering of the integrated circuit, said power supply terminals including a V dd positive supply terminal and a V ss ground terminal together defining a range of logic levels;
cells, each said cells being a selected one of a logic gate and a storage cell, and each said cells including a sleep transistor in series with each electrical connection to one of said power supply terminals;
generator circuitry for generating a voltage outside said range of logic levels; and
additional circuitry for applying, in a power down mode, said generated voltage to said sleep transistors of said cells.
2. The integrated circuit as claimed in claim 1 wherein said one of the power supply terminals is the V ss terminal, said voltage outside the range of logic levels is a voltage lower than V ss , and said sleep transistor is an n-channel transistor.
3. The integrated circuit as claimed in claim 2 wherein said additional circuitry applies V dd to said sleep transistor when in another mode than said power down mode.
4. The integrated circuit as claimed in claim 2 wherein said additional circuitry applies a voltage greater than V dd to said sleep transistor when in another mode than said power down mode.
5. The integrated circuit as claimed in claim 1 wherein said one of the power supply terminals is the V dd terminal, said generated voltage is a voltage higher than V dd , and said sleep transistor is a p-channel transistor.
6. The integrated circuit as claimed in claim 5 wherein said additional circuitry applies V ss to said sleep transistor when not in a power down mode.
7. The integrated circuit as claimed in claim 5 wherein said additional circuitry applies a voltage less than V ss to said sleep transistor when not in a power down mode.
8. The integrated circuit as claimed in claim 1 wherein said cells include inverters.
9. The integrated circuit as claimed in claim 1 wherein said cells include flip-flops.
10. The integrated circuit as claimed in claim 1 wherein said sleep transistor has a similar gate thickness as other transistors in the cell.
11. The integrated circuit as claimed in claim 10 wherein said sleep transistor and the other transistors are thin gate devices.
12. The integrated circuit as claimed in claim 1 wherein said additional circuitry applies the voltage from a first of the power supply terminals to said sleep transistor when in another mode than said power down mode.
13. The integrated circuit as claimed in claim 1 wherein said generator circuitry comprises a sleep generator.
14. The integrated circuit as claimed in claim 13 wherein said sleep generator comprises a charge pump circuit.
15. The integrated circuit as claimed in claim 1 wherein said sleep transistor has a similar threshold voltage as other transistors in the cell.
16. The integrated circuit as claimed in claim 15 wherein said sleep transistor is a regular threshold voltage transistor.
17. A storage cell in an integrated circuit, the integrated circuit having a power manager, a V dd positive supply terminal and a V ss ground supply terminal, the two supply terminals in electrical communication with the storage cell, the storage cell comprising:
a sleep transistor in series with each electrical connection to one of the supply terminals, said sleep transistor adapted to be turned off by the power manager when in a power down mode; and
a source follower transistor in parallel with said sleep transistor in portions of the storage cell which retain binary data in said power down mode,
whereby said storage cell stores said binary data.
18. The storage cell as claimed in claim 17 wherein said one of the power supply terminals is the V ss terminal and said sleep transistor is an n-channel transistor.
19. The storage cell as claimed in claim 18 wherein said source follower transistor is a p-channel transistor with its gate connected to V ss .
20. The storage cell as claimed in claim 18 wherein said sleep transistor is adapted to receive V dd from the power manager when in another mode than said power down mode.
21. The storage cell as claimed in claim 18 wherein said sleep transistor is adapted to receive a voltage lower than V ss from the power manager when in said power down mode.
22. The storage cell as claimed in claim 18 wherein said sleep transistor is adapted to receive a voltage greater than V dd from the power manager when in another mode than said power down mode.
23. The storage cell as claimed in claim 17 wherein the storage cell is a flip-flop.
24. The storage cell as claimed in claim 23 wherein portions of said flip-flop which retain said binary data in said power down mode include the slave latch portion of said flip-flop.
25. The storage cell as claimed in claim 17 wherein said sleep transistor is adapted to receive a voltage, from a first of the supply terminals, from the power manager when in another mode than said power down mode.
26. The storage cell as claimed in claim 17 wherein said sleep transistor is adapted to receive a voltage, outside the range of logic levels defined by the two supply terminals, from the power manager when in said power down mode.
27. The storage cell as claimed in claim 17 wherein said sleep transistor and said source follower transistor have similar threshold voltages as other transistors in the storage cell.
28. The storage cell as claimed in claim 27 wherein said sleep transistor and said source follower transistor are low threshold voltage transistors.
29. The storage cell as claimed in claim 17 wherein the gate of said source follower transistor is electrically connected to said one of the supply terminals.
30. The storage cell as claimed in claim 17 wherein said source follower transistor has a polarity opposite to that of said sleep transistor.
31. A storage cell in an integrated circuit, the integrated circuit having a power manager, a V dd positive supply terminal and a V ss ground supply terminal, the two supply terminals in electrical communication with the storage cell, the storage cell comprising:
stacked transistors in portions of the storage cell which retain binary data in a power down mode;
a sleep transistor in series with each electrical connection to one of the supply terminals in remaining portions of the storage call, which are non-retaining portions, and said sleep transistor adapted to be turned off by the power manager when in a power down mode, and
whereby said storage cell stores said binary data.
32. The storage cell as claimed in claim 31 wherein said one of the power supply terminals is the V ss terminal and said sleep transistor is an n-channel transistor.
33. The storage cell as claimed in claim 32 wherein said sleep transistor is adapted to receive V dd from the power manager when in another mode than said power down mode.
34. The storage cell as claimed in claim 32 wherein said sleep transistor is adapted to receive a voltage lower than V ss from the power manager when in said power down mode.
35. The storage cell as claimed in claim 32 wherein said sleep transistor is adapted to receive a voltage greater than V dd from the power manager when in another mode than said power down mode.
36. The storage cell as claimed in claim 31 wherein said stacked transistors are n-channel stacked transistors.
37. The storage cell as claimed in claim 31 wherein said stacked transistors are p-channel stacked transistors.
38. The storage cell as claimed in claim 31 wherein the storage cell is a flip-flop.
39. The storage cell as claimed in claim 38 wherein portions of said flip-flop which retain said binary data in said power down mode include the slave latch portion of said flip-flop.
40. The storage cell as claimed in claim 31 wherein said sleep transistor is adapted to receive a voltage, from a first of the supply terminals, from the power manager when in another mode than said power down mode.
41. The storage cell as claimed in claim 31 wherein said sleep transistor is adapted to receive a voltage, outside the range of logic levels defined by the two supply terminals, from the power manager when in said power down mode.
42. The storage cell as claimed in claim 31 wherein said sleep transistor and said stacked transistors have similar threshold voltages as other transistors in the storage cell.
43. The storage cell as claimed in claim 42 wherein said sleep transistor and said stacked transistors are low threshold voltage transistors.
44. A power management method comprising:
operating an integrated circuit having cells, each of the cells being a selected one of a logic gate and a storage cell, and each of the cells including a sleep transistor in series with each electrical connection to a selected one of a V dd positive supply terminal and a V ss ground terminal, the V dd positive supply terminal and the V ss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including:
generating a voltage outside said range of logic levels; and
applying, in a power down mode, said generated voltage to the sleep transistors of said cells.
45. The power management method as claimed in claim 44 wherein the selected one of terminals is the V ss terminal, said voltage outside the range of logic levels is a voltage lower than V ss , and said sleep transistor is an n-channel transistor.
46. The power management method as claimed in claim 45 wherein said operating of the integrated circuit further includes applying V dd to said sleep transistor when in another mode than said power down mode.
47. The power management method as claimed in claim 45 wherein said operating of the integrated circuit further includes applying a voltage greater than V dd to said sleep transistor when in another mode than said power down mode.