High bandwidth memory interface
View Patent ↗This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.
1. A semiconductor device comprising:
a) memory;
b) a plurality of terminals for coupling to a bus including a free running clock input terminal, a data clock output terminal and data output terminals, the data output terminals providing output data from the memory;
c) a clock generator for driving a data clock output signal on the data clock output terminal in synchronization with said output data in response to a free running clock signal at the free running clock input terminal;
d) output drivers for driving said output data to said bus; and
e) a termination resistor coupled to one of said data output terminals.
2. The semiconductor device as claimed in claim 1 , wherein said memory is a Dynamic Random Access Memory (DRAM).
3. The semiconductor device as claimed in claim 2 , wherein said termination resistor is part of a package substrate, and said DRAM is a semiconductor memory chip mounted on said package substrate.
4. The semiconductor device as claimed in claim 3 , wherein said termination resistor is a series stub termination resistor.
5. The semiconductor device as claimed in claim 3 , wherein said termination resistor is a film resistor deposited on said package substrate.
6. The semiconductor device as claimed in claim 2 , wherein said DRAM and said termination resistor are integrated on a semiconductor memory chip.
7. The semiconductor device as claimed in claim 6 , wherein said termination resistor is a series stub termination resistor.
8. The semiconductor device as claimed in claim 2 , wherein said output drivers are open-drain drivers.
9. The semiconductor device as claimed in claim 2 , wherein said output drivers are push-pull drivers.
10. The semiconductor device as claimed in claim 2 , wherein said termination resistor is a series stub termination resistor.
11. The semiconductor device as claimed in claim 2 , wherein said data clock output terminal is a data clock input/output terminal, and said data output terminals are data input/output terminals.
12. The semiconductor device as claimed in claim 2 , wherein said clock generator is a source synchronous clock generator.
13. The semiconductor device as claimed in claim 1 , wherein said memory and said termination resistor are integrated on a semiconductor memory chip.
14. The semiconductor device as claimed in claim 13 , wherein said termination resistor is a series stub termination resistor.
15. A semiconductor device comprising:
a) memory;
b) a plurality of terminals for coupling to a bus including a free running clock input terminal, a data clock input/output terminal and data input/output terminals, the data input/output terminals providing output data from the memory;
c) a clock generator for driving a data clock output signal on the data clock input/output terminal in synchronization with said output data in response to a free running clock signal at the free running clock input terminal;
d) output drivers for driving said output data to said bus; and
e) a termination resistor coupled to one of said data input/output terminals.
16. The semiconductor device as claimed in claim 15 , wherein said memory is a Dynamic Random Access Memory (DRAM).
17. The semiconductor device as claimed in claim 16 , wherein said DRAM and said termination resistor are integrated on a semiconductor memory chip.
18. The semiconductor device as claimed in claim 17 , wherein said termination resistor is a series stub termination resistor.
19. The semiconductor device as claimed in claim 16 , wherein said clock generator is a source synchronous clock generator.
20. The semiconductor device as claimed in claim 16 , wherein said output drivers are open-drain drivers.
21. The semiconductor device as claimed in claim 16 , wherein said output drivers are push-pull drivers.
22. The semiconductor device as claimed in claim 16 , wherein said termination resistor is a series stub termination resistor.
23. The semiconductor device as claimed in claim 16 , wherein said termination resistor is part of a package substrate, and said DRAM is a semiconductor memory chip mounted on said package substrate.
24. The semiconductor device as claimed in claim 23 , wherein said termination resistor is a series stub termination resistor.
25. The semiconductor device as claimed in claim 23 , wherein said termination resistor is a film resistor deposited on said package substrate.
26. The semiconductor device as claimed in claim 15 , wherein said memory and said termination resistor are integrated on a semiconductor memory chip.
27. The semiconductor device as claimed in claim 26 , wherein said termination resistor is a series stub termination resistor.