Semiconductor integrated circuit having current leakage reduction scheme
View Patent ↗A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor. The power gating to the CMOS inverter is performed by feedback of the output signal and the complementary input signal, with the result that current leakage reduction through the CMOS controlled inverter is achieved. A self leakage reduction with power gating transistors is applicable to another type of logic gates such as NAND, NOR and Exclusive-OR, AND, OR.
1. A semiconductor integrated circuit (IC) operated with “high” and “low” level power supply voltages, the semiconductor IC comprising:
a logic gate for providing an output logic signal in response to at least one input logic signal;
a control circuit for providing a feedback control signal in response to the output logic signal and an additional input logic signal;
a power gate for selectively gating power to the logic gate in response to the feedback control signal; and
an adjustable delay circuitry for providing the additional input logic signal at a time interval after receiving a complementary signal of the at least one input logic signal.
2. The semiconductor IC of claim 1 , wherein the additional input logic signal is derived from the input logic signal with different logic transition timing.
3. The semiconductor IC of claim 2 , wherein the logic gate circuit comprises a logic circuit for performing an inverting function, the at least one input logic signal comprising one input logic signal, the output logic signal being an inverted signal of the input logic signal.
4. The semiconductor IC of claim 2 , wherein the logic gate circuit comprises a logic circuit for performing a logic function to logically combine a plurality of logic signals, the at least one input logic signal comprising at least two input logic signals, the output logic signal being output of logically combined input signals.
5. The semiconductor IC of claim 3 , wherein the logic gate circuit comprises:
a CMOS inverter including a first PMOS transistor and a first NMOS transistor that are series-coupled, a first input logic signal being provided to the gates of the series-coupled first PMOS and NMOS transistors, the coupled node of which provides an output logic signal that
is a complementary version of the input logic signal, a feedback signal derived from the output logic signal being provided to the logic gate circuit to control the operation thereof.
6. The semiconductor IC of claim 5 , wherein the power gating circuit comprises: a second NMOS transistor, the drain of which is coupled to the source of the first NMOS transistor, the low power level voltage being provided to the source of the second NMOS transistor, the high power level voltage being provided to the source of the first PMOS transistor, the gate of the second NMOS transistor responding to the feedback signal.
7. The semiconductor IC of claim 6 , wherein the control circuit comprises a logic gate for providing the feedback signal in response to the output logic signal and the additional input logic signal.
8. The semiconductor IC of claim 7 , wherein the additional input logic signal is a complementary version of the first input logic signal, the logic level transition timings of the first and the additional logic being different, each of the first and the additional input logic signals having first and second direction transitions, the second direction transition being opposite to the first direction transition.
9. The semiconductor IC of claim 8 , wherein the first and second direction transitions are rising and falling transitions, respectively, the rising transition of the first input logic signal being later than the falling transition of the additional input signal by a time interval.
10. The semiconductor IC of claim 9 , wherein the logic gate comprises a NAND gate for providing the feedback signal in response to the output logic signal and the additional input logic signal.
11. The semiconductor IC of claim 5 , wherein the power gating comprises: a second PMOS transistor, the drain of which is coupled to the source of the first PMOS transistor, the high power level voltage being provided to the source of the second PMOS transistor, the gate of the second PMOS transistor responding to the feedback signal.
12. The semiconductor IC of claim 11 , wherein the control circuit comprises a logic gate for providing the feedback signal in response to the output logic signal and the additional input logic signal.