Low power memory architecture
A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.
1. A low power memory array comprising:
two or more memory subdivisions having dynamic random access (DRAM) memory cells connected to bitlines;
a global power supply voltage received by the two or more memory subdivisions;
a local power grid in each of the two or more memory subdivisions for selectively distributing the global power voltage;
a power gating circuit in each of the two or more memory subdivisions for selectively connecting the global power voltage to the corresponding local power grid of one of the two or more memory; and,
bitline sense amplifiers connected to the bitlines, each of the bitline sense amplifiers having at least one transistor for selectively coupling the global power voltage of the local power grid to a corresponding bitline sense amplifier for sensing data stored in respective DRAM cells in the one of the two or more memory subdivisions.
2. The low power memory array of claim 1 , wherein each of the two or more memory subdivisions include datapath circuitry connected to the local power grid.
3. The low power memory array of claim 2 , wherein the datapath circuitry includes bitline sense amplifiers.
4. The low power memory array of claim 1 , wherein the power gating circuit selectively connects the global power voltage to the corresponding local power grid of one of the two or more memory subdivisions in response to a decoded address signal.
5. The low power memory array of claim 1 , wherein the global power voltage includes a logic high global power supply voltage and a logic low global power supply voltage.
6. The low power memory array of claim 5 , wherein the local power grid includes a first local power grid for distributing the logic high global power supply voltage, and a second local power grid for distributing the logic low global power supply voltage.
7. The low power memory array of claim 6 , wherein the power gating circuit includes a first power switch transistor connected between the logic high global power supply voltage and the first local power grid, and a second power switch transistor connected between the logic low global power supply voltage and the second local power grid.
8. The low power memory array of claim 1 , wherein the low power memory array is formed in a discrete dynamic random access memory device.
9. The low power memory array of claim 1 , wherein the low power memory array is embedded in a semiconductor device.
10. The low power memory array of claim 9 , wherein the semiconductor device includes one of a microprocessor, a digital signal processor (DSP) and an application specific integrated circuit (ASIC).
11. A method for low power operation of a memory array, the memory array being arranged in subdivisions each having local power grids, comprising:
a) receiving a memory access command for accessing at least one of the subdivisions, the subdivisions including dynamic random access memory (DRAM) cells;
b) connecting a global power supply voltage to the local power grid of the at least one subdivision to be accessed;
c) connecting the global power supply voltage of the local power grid to bitline sense amplifiers of the at least one subdivision to be accessed; and;
d) sensing data stored in respective DRAM cells of the at least one subdivision to be accessed with the bitline sense amplifiers.
12. The method of claim 11 , wherein the step of connecting includes activating a power switch transistor for connecting the global power supply voltage to the local power grid.
13. The method of claim 11 , further including executing the memory access command in the at least one subdivision after the step of connecting.
14. The method of claim 13 , further including disconnecting the global power supply voltage from the local power grid of the at least one subdivision after the step of executing.
15. The method of claim 11 , wherein the global power supply voltage includes logic high and a logic low supply voltages and the local power grid includes logic high and logic low local power grids.
16. The method of claim 15 , wherein the step of connecting includes activating a power switch transistor for connecting the logic high supply voltage to the local logic high power grid and for connecting the logic low supply voltage to the local low power grid.