Flash memory program inhibit scheme
View Patent ↗A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
1. A method for minimizing program disturb in NAND string having a selected memory cell, upper memory cells between the selected memory cell and a bitline, lower memory cells between the selected memory cell and a sourceline, and a string select transistor for coupling the memory cells to the bitline, comprising:
a) in a first time period, coupling a voltage level corresponding to program inhibit voltage from the bitline to the NAND string;
b) in a second time period following the first time period, precharging channels of the selected memory cell and the upper memory cells to a primary boosted voltage level after the voltage level is coupled to the channel of the NAND string by driving a selected wordline connected to the selected memory cell and upper wordlines connected to the upper memory cells to a first pass voltage level, and driving lower wordlines connected to the lower memory cells to a second pass voltage, the second pass voltage being less than the first pass voltage; and,
c) in a third time period following the second time period, locally boosting the selected memory cell channel to a secondary boosted voltage level after the channel is precharged, the secondary boosted voltage level being higher than the primary boosted voltage level by driving the selected wordline connected to the selected memory cell to a programming voltage level, and electrically turning off an upper memory cell adjacent to the selected memory cell.
2. The method for minimizing program disturb of claim 1 , wherein the step of coupling includes driving the string select transistor to a first voltage level in the first time period, followed by driving the string select transistor to a decoupling voltage level in the second time period, the decoupling voltage level being lower than the first voltage level.
3. The method for minimizing program disturb of claim 1 , wherein the first pass voltage is less than 10 volts.
4. The method for minimizing program disturb of claim 3 , wherein the first pass voltage is approximately 7 volts.
5. The method for minimizing program disturb of claim 1 , wherein the first pass voltage has a value effective for minimizing program disturb in the upper memory cells and for maximizing the primary boosted voltage level.
6. The method for minimizing program disturb of claim 1 , wherein the step of driving the selected wordline includes driving the selected wordline to the programming voltage level after the upper memory cell adjacent to the selected memory cell is turned off.
7. The method for minimizing program disturb of claim 1 , wherein the step of electrically turning off includes reducing an upper wordline connected to the upper memory cell from the first pass voltage level to a decoupling voltage level while the selected wordline is driven to the programming voltage level.
8. The method for minimizing program disturb of claim 1 , wherein the step of electrically turning off includes reducing an upper wordline connected to the upper memory cell from the first pass voltage level to a decoupling voltage level, and driving the selected wordline to the programming voltage level at a predetermined delay time after the upper wordline begins to drop towards the decoupling voltage level.
9. The method for minimizing program disturb of claim 1 , wherein the step of electrically turning off includes increasing the upper wordlines except the upper wordline adjacent to the selected wordline, from the first pass voltage level to a second pass voltage while the selected wordline is driven to the programming voltage level, the upper wordline adjacent to the selected wordline being maintained at the first pass voltage level.
10. The method for minimizing program disturb of claim 1 , wherein the step of locally boosting includes reducing a lower wordline adjacent to the selected wordline from the second pass voltage to an off voltage level while the selected wordline is driven to the programming voltage level.
11. The method for minimizing program disturb of claim 1 , wherein the step of precharging includes driving lower wordlines connected to the lower memory cells except for a lower wordline adjacent to the selected wordline to a second pass voltage, the lower wordline adjacent to the selected wordline being maintained at an off voltage level during the first time period, the second time period and the third time period.
12. The method for minimizing program disturb of claim 1 , further including iteratively increasing the programming voltage level by predetermined voltage steps while maintaining the first pass voltage level and the second pass voltage level.
13. A method for minimizing program disturb in a Flash memory NAND string, the NAND string having a selected memory cell, upper memory cells between the selected memory cell and a bitline, lower memory cells between the selected memory cell and a source line, and a string select transistor for coupling the memory cells to the bitline, comprising:
a) driving the string select transistor for coupling data voltage of the bitline to the NAND string in a first time period;
b) driving the upper memory cells and the selected memory cell with a pass voltage level in a second time period;
c) driving the lower memory cells except a lower memory cell adjacent to the selected memory cell with a second pass voltage level in the second time period, the second pass voltage level being lower than the pass voltage;
d) driving the selected memory cell to a program voltage level in a third time period; and
e) electrically turning off the upper memory cell adjacent to the selected memory cell in the third time period.
14. The method for minimizing program disturb of claim 13 , wherein the lower memory cell is driven to 0V during the second time period.
15. The method for minimizing program disturb of claim 13 , wherein the lower memory cell is driven with the second pass voltage level in the second time period.
16. The method for minimizing program disturb of claim 15 , further including driving a lower memory cell adjacent to the selected memory cell with an off voltage level in the third time period.
17. The method for minimizing program disturb of claim 13 , wherein the step of electrically turning off includes driving an upper memory cell adjacent to the selected memory cell from the pass voltage level to a decoupling voltage while the selected memory cell is driven to the programming voltage level in the third time period.
18. The method for minimizing program disturb of claim 17 , wherein the selected memory cell is driven to the programming voltage level at a delay time after the upper memory cell adjacent to the selected memory cell starts to be driven to the decoupling voltage.
19. The method for minimizing program disturb of claim 13 , wherein the step of electrically turning off includes driving the upper memory cells except an upper memory cell adjacent to the selected memory cell from the pass voltage to a second pass voltage in the third time period, the second pass voltage being greater than the pass voltage.
20. The method for minimizing program disturb of claim 13 , further including iteratively increasing the program voltage level by predetermined voltage steps while maintaining the pass voltage level and the off voltage level.