Embedded memory databus architecture
View Patent ↗A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
1. An application specific integrated circuit (ASIC) device comprising a DRAM, the DRAM comprising:
a) a plurality of memory arrays including:
i) word lines extending in a first direction,
ii) bit lines organized in groups and extending in a second direction orthogonal to the first direction, and
iii) charge storage cells formed at intersections of said word lines and said bit lines;
b) a plurality of strips of bit line sense amplifiers electrically connected to said bit lines;
c) a plurality of data bus lines extending in the second direction;
d) a plurality of selection circuitries, each said plurality of selection circuitries configured to connect a sense amplifier associated with a bit line of a respective one of said groups of bit lines to a respective one of said plurality of data bus lines that is adjacent the respective one of the groups; and
e) a plurality of data bus read amplifiers electrically connected to said data bus lines and configured to facilitate transmission of first data to outputs of said DRAM, and
said DRAM is embedded within the ASIC device.
2. The ASIC device as claimed in claim 1 , wherein the transmission of first data to outputs of said DRAM is accomplished without Y-decoding.
3. The ASIC device as claimed in claim 2 , wherein the plurality of memory arrays and the plurality of strips of bit line sense amplifiers are equal in number.
4. The ASIC device as claimed in claim 2 , wherein each group of bitlines comprises four bit lines.
5. The ASIC device as claimed in claim 2 , wherein each group of bitlines comprises two bit lines.
6. The ASIC device as claimed in claim 2 , wherein sense amplifiers are directly connected to bit lines.
7. The ASIC device as claimed in claim 2 , wherein said data bus lines comprise complementary data bus pairs.
8. The ASIC device as claimed in claim 7 , wherein said bit lines comprise complementary bit line pairs.
9. The ASIC device as claimed in claim 2 , wherein said bit lines comprise complementary bit line pairs.
10. The ASIC device as claimed in claim 1 , wherein said bit lines comprise complementary bit line pairs.
11. The ASIC device as claimed in claim 10 , wherein said data bus lines comprise complementary data bus pairs.
12. The ASIC device as claimed in claim 1 , further comprising a plurality of data bus write amplifiers electrically connected to said data bus lines and configured to receive second data from inputs of said DRAM.
13. The ASIC device as claimed in claim 12 , further comprising a plurality of data bus write amplifiers electrically connected to said data bus lines for providing write data from an input of said embedded DRAM to the memory arrays.
14. The ASIC device as claimed in claim 13 , wherein the transmission of said first data to outputs of said DRAM is accomplished without Y-decoding.
15. The ASIC device as claimed in claim 12 , wherein the transmission of said first data to outputs of said DRAM is accomplished without Y-decoding.
16. The ASIC device as claimed in claim 1 , wherein each said plurality of selection circuitries receives a respective array select signal.
17. The ASIC device as claimed in claim 16 wherein said selection circuitries comprises FET devices controlled by array select signals, the FET devices being electrically connected between sense amplifiers of the strips and said data bus lines.
18. The ASIC device as claimed in claim 17 , wherein said selection circuitries comprises single FET devices having source/drain current carrying electrodes directly connected between sense amplifiers of the strips and said data bus lines.
19. The ASIC device as claimed in claim 16 , wherein said selection circuitries comprises FET devices with respective gates controlled by array select signals, and source/drain current carrying electrodes being electrically connected between sense amplifiers of the strips and said data bus lines.
20. The ASIC device as claimed in claim 1 , wherein a pair of the data bus lines extend along opposite sides of a row of said sense amplifiers.
21. An application specific integrated circuit (ASIC) device comprising a DRAM, the DRAM comprising:
a) a plurality of memory arrays including:
i) word lines extending in a first direction,
ii) bit lines organized in groups and extending in a second direction orthogonal to the first direction, and
iii) charge storage cells formed at intersections of said word lines and said bit lines;
b) a plurality of strips of bit line sense amplifiers electrically connected to said bit lines;
c) a plurality of data bus lines extending in the second direction;
d) a plurality of selection circuitries, each said plurality of selection circuitries configured to connect a sense amplifier associated with a bit line of a respective one of said groups of bit lines to a respective one of said plurality of data bus lines that is adjacent the respective one of the groups; and
e) a plurality of data bus write amplifiers electrically connected to said data bus lines and configured to apply first data from inputs of said DRAM to said data bus lines, and
said DRAM is embedded within the ASIC device.
22. The ASIC device as claimed in claim 21 , wherein the transmission of first data from inputs of said DRAM is accomplished without Y-decoding.
23. The ASIC device as claimed in claim 22 , wherein the plurality of memory arrays and the plurality of strips of bit line sense amplifiers are equal in number.
24. The ASIC device as claimed in claim 22 , wherein each group of bitlines comprises four bit lines.
25. The ASIC device as claimed in claim 22 , wherein each group of bitlines comprises two bit lines.
26. The ASIC device as claimed in claim 22 , wherein sense amplifiers are directly connected to bit lines.
27. The ASIC device as claimed in claim 22 , wherein said data bus lines comprise complementary data bus pairs.
28. The ASIC device as claimed in claim 27 , wherein said bit lines comprise complementary bit line pairs.
29. The ASIC device as claimed in claim 22 , wherein said bit lines comprise complementary bit line pairs.
30. The ASIC device as claimed in claim 21 , wherein said bit lines comprise complementary bit line pairs.
31. The ASIC device as claimed in claim 30 , wherein said data bus lines comprise complementary data bus pairs.
32. The ASIC device as claimed in claim 21 , further comprising a plurality of data bus read amplifiers electrically connected to said data bus lines and configured to receive second data from said databus lines.
33. The ASIC device as claimed in claim 32 , further comprising a plurality of data bus read amplifiers electrically connected to said data bus lines for providing read data from said databus lines to an output of said embedded DRAM.
34. The ASIC device as claimed in claim 33 , wherein the transmission of said first data to outputs of said DRAM is accomplished without Y-decoding.
35. The ASIC device as claimed in claim 32 , wherein the transmission of said first data to outputs of said DRAM is accomplished without Y-decoding.
36. The ASIC device as claimed in claim 21 , wherein each said plurality of selection circuitries receives a respective array select signal.
37. The ASIC device as claimed in claim 36 wherein said selection circuitries comprises FET devices controlled by array select signals, the FET devices being electrically connected between sense amplifiers of the strips and said data bus lines.
38. The ASIC device as claimed in claim 37 , wherein said selection circuitries comprises single FET devices having source/drain current carrying electrodes directly connected between sense amplifiers of the strips and said data bus lines.
39. The ASIC device as claimed in claim 36 , wherein said selection circuitries comprises FET devices with respective gates controlled by array select signals, and source/drain current carrying electrodes being electrically connected between sense amplifiers of the strips and said data bus lines.
40. The ASIC device as claimed in claim 21 , wherein a pair of the data bus lines extend along opposite sides of a row of said sense amplifiers.