Timing vernier using a delay locked loop
View Patent ↗A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.
1. A method for generating timing signals with fine resolution time delay said fine resolution time delay being a predetermined fraction of a reference time said reference time being time between two transitions of reference signals comprising the steps of:
(a) providing a first and a second control vernier;
(b) programming said first control vernier to a first number of delay steps;
(c) programming said second control vernier to a second number of delay steps;
(d) applying a start signal simultaneously to inputs of said first and second control verniers to obtain first and second delay signals respectively at first and second control vernier outputs;
(e) generating a difference signal corresponding to a difference between said first delay signal and second delay signal;
(f) comparing the difference signal to a reference signal to generate a control signal, said control signal being coupled to a bias input of said control verniers to continuously adjust a value of delay step of the control verniers; and
(g) coupling said control signal to bias inputs of a plurality of timing signal generating verniers to continuously adjust values of delay steps of the timing signal generating verniers.
2. The method as claimed in claim 1 , providing verniers comprising delay lines with variable value of the delay steps that are programmable to vary the number of the delay steps.
3. The method as claimed in claim 2 , wherein said value of the delay step is determined by applying a voltage to the control signal input of the timing signal generating verniers.
4. The method as claimed in claim 2 , wherein said number of delay steps is determined by a value of a digital code applied to programming inputs of the verniers.
5. The method as claimed in claim 4 , wherein programming said verniers comprises applying said digital code to said programming inputs of said verniers.
6. The method as claimed in claim 2 , further comprising providing delay lines comprising a plurality of similar delay stages connected in series with intermediate delay line outputs tapped between said delay stages.
7. The method as claimed in claim 1 , wherein providing said first and second control verniers comprises providing similar first and second control verniers.
8. The method as claimed in claim 1 , further comprising providing said timing signal generating verniers that are similar to said first and second control verniers.
9. The method as claimed in claim 1 , wherein said first number of the delay steps is smaller then said second number of the delay steps.
10. The method as claimed in claim 1 , wherein said predetermined fraction of a reference time is determined by deriving difference between said first number of the delay steps and said second number of the delay steps.
11. The method as claimed in claim 1 , further comprising using a feedback loop to provide said continuous adjustment of the values of the delay steps of the verniers.
12. The method as claimed in claim 11 , wherein said feedback loop comprises a delay locked loop.
13. The method as claimed in claim 1 , wherein said timing signals comprise timing pulses.
14. The method as claimed in claim 13 , wherein a pulse width of the timing pulses is a determined fraction of the reference time.
15. The method as claimed in claim 13 , further comprising obtaining said timing pulses using intermediate delay line output signals.
16. The method as claimed in claim 1 , wherein said reference signals applied to said control verniers and said reference signals applied to said plurality of said timing signals generating verniers are substantially the same signals.
17. The method as claimed in claim 1 , wherein said reference signals applied to said plurality of said timing signal generating verniers are derived from said reference signals applied to said control verniers.
18. The method as claimed in claim 1 , wherein said transitions of said reference signal comprise rising edges.
19. A method as claimed in claim 1 , wherein said transitions of the reference signal comprise falling edges.
20. The method as claimed in claim 1 , said reference time is equal to one or more periods of a global clock signal.