Method and apparatus for replacing defective rows in a semiconductor memory array
View Patent ↗A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row match line input, repeating the switching for subsequent matchlines upto the matchline of the at least one spare row.
1. A method for replacing a defective row in a content addressable memory (CAM) array having a plurality of memory block arrays, said arrays having a plurality of normal rows of cells and at least one spare row of cells, each said row being enabled by a corresponding wordline signal, and having corresponding match line outputs switchable to corresponding ones of a plurality of match line inputs in a match line decoder, said method comprising the steps of:
(a) generating a signal indicative of the location of a defective row in at least one of said arrays;
(b) generating a set of word line select signals for selecting ones of said plurality of normal rows;
(c) using said defective row signal to switch a word line select signal of said defective row to a row adjacent said defective row and switching said adjacent row word line select signals to subsequent rows up to said at least one spare row, and
(d) using said defective row signal to switch the match line output of said row adjacent said defective row to the match line input of said defective row and switching said subsequent row match line output to said adjacent row match line input, repeating said switching for subsequent match lines up to said match line of said at least one spare row.
2. The method according to claim 1 , wherein generating said signal indicative of the location of a defective row, includes programming a fuse bank with the location of the defective row.
3. The method according to claim 1 , comprising programming a fuse bank in order to generate a fuse encoded signal and combining said fuse encoded signal with a normal address signal to generate said signal indicative of the location of said defective row.
4. The method according to claim 1 , wherein generating said set of word line select signals comprises generating local word line select signals and global word line select signals and combining corresponding ones of said local word line select signals and said global word line select signals to generate said set of word line select signals.
5. A content addressable memory array, comprising:
(a) a plurality of memory blocks; each block comprising:
(i) a plurality of memory cells arranged in rows, said rows including a plurality of normal rows and at least one spare row, each row having a match line coupled to said memory cells in said row, said match line for providing a match line output signal indicative of a comparison result;
(ii) a match line, decoder for selecting a plurality of match line signals to output, each aid match line signal to output being selected from one of two adjacent rows; and
(iii) a sense amplifier coupled to said match line said sense amplifier for providing said comparison result at a sense amplifier output; and
(b) a row select decoder for generating a plurality of word line select signals corresponding to said rows, each word line select signal selectively coupled to one of two adjacent rows.
6. The content addressable memory array according to claim 5 , comprising a programmable bank for storing the location of at least one defective row, said programmable bank being coupled to said row select decoder in order to disable said at least one defective row.
7. The content addressable memory array according to claim 6 , wherein said programmable bank is a programmable fuse bank.
8. The content addressable memory array according to claim 5 , comprising a priority encoder having a plurality of match line inputs, said match line inputs coupled to said match line output signals selected by said match line decoder.
9. The content addressable memory array according to claim 8 , wherein the number of match line inputs correspond to the number of normal rows in said content addressable memory array.
10. The content addressable memory array according to claim 8 , further comprising a latch for latching said sense amplifier output.
11. The content addressable memory array according to claim 5 , comprising for each row, a local word line and a global word line, said local word line and said global word line for generating a pair of signals that are combined to generate said word line select signal.
12. The content addressable memory array according to claim 5 , wherein said at least one spare row is located at one end of the content addressable memory array.