Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
View Patent ↗A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
1. A dynamic random access memory (DRAM) device comprising:
an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column; and
a refresh circuit for controlling a data refresh rate of the DRAM cells corresponding to a basic time period in a self-refresh mode, the refresh circuit comprising:
a mode detection circuit for detecting an entry into and an exit from the self-refresh mode to provide a self-refresh mode signal;
an oscillation circuit for producing an oscillation signal in response to the self-refresh mode signal to provide the basic time period; and
a refresh time change circuit for changing the basic time period in response to one of two refresh time change factors, the factors including a process variation factor relating to the DRAM device and a temperature change factor relating to the DRAM device to provide a changed time period and further changing the changed time period in response to the other refresh time change factor, to provide a further changed time period for self-refreshing.
2. The DRAM device of claim 1 , wherein the refresh time change circuit comprises:
a first changing circuit for changing the repetition period of the oscillation signal in response to the one refresh time change factor to provide a first period changed signal having the changed time period and
a second changing circuit for changing the repetition period of the first period changed signal in response to the other refresh time change factor to provide a second period changed signal having the further changed time period.
3. The DRAM device of claim 2 , wherein:
the first changing circuit comprises:
a first frequency producing circuit for producing a first set of m frequency signals in response to the oscillation signal having an oscillation frequency, each of the m frequency signals having a different frequency relating to the oscillation frequency, m being an integer greater than one; and
a first selection circuit for selecting one signal from the first set of m frequency signals, so that the selected signal is provided as the first period changed signal, and the second changing circuit comprises:
a second frequency producing circuit for producing a second set of n frequency signals in response to the first period changed signal, each of the n frequency signals having a different frequency relating to the oscillation signal, n being an integer greater than one; and
a second selection circuit for selecting one signal from the second set of n frequency signals, so that the selected signal is provided as the second period changed signal.
4. The DRAM device of claim 3 , wherein:
the first frequency producing circuit comprises:
a first frequency dividing circuit for dividing the oscillation frequency in accordance with a first parameter to produce the first set of m frequency signals, so that the first selection circuit selects one signal of the m divided different frequency signals, and
the second frequency producing circuit comprises:
a second frequency dividing circuit for dividing the frequency of the first period changed signal in accordance with a second parameter to produce the second set of n frequency signals, so that the second selection circuit selects one signal of the n divided different frequency signals.
5. The DRAM device of claim 4 , further comprising:
a factor providing circuit for providing the factor of process variations relating to the DRAM device and the temperature changes relating to the DRAM device.
6. The DRAM device of claim 5 , wherein the factor providing circuit comprises:
a first factor provider for designating the first parameter, so that the first frequency producing circuit divides the frequency of the oscillation signal in accordance with the designated first parameter; and
a second factor provider for designating the second parameter, so that the second frequency producing circuit divides the frequency of the first period divided signal in accordance with the designated second parameter.
7. The DRAM device of claim 6 , wherein:
the first factor provider comprises:
a process variation provider for providing a process variation code for designating the first parameter, the process variation code being derived from the process variations comprising DRAM characteristics, and
the second factor provider comprises:
a temperature change provider for providing a temperature change code for designating the second parameter, the temperature change code being derived from temperature changes comprising temperature sensed from the DRAM device.
8. The DRAM device of claim 7 , wherein:
the process variation provider comprises:
a first generator for generating the process variation code representing a plurality of variations of the DRAM characteristics, and
the temperature change provider comprises:
a second generator for generating the temperature change code representing a plurality of temperature changes of sensed temperature variations.
9. The DRAM device of claim 8 , wherein:
the first generator comprises:
a first decoder for decoding the plurality of variations and providing the process variation code, and
the second generator comprises:
a second decoder for decoding the plurality of temperature changes and providing the temperature change code.
10. The DRAM device of claim 9 , wherein:
the first selection circuit comprises:
a first signal selection circuit for selecting one of the m divided frequencies of the first set of frequency signals to provide the selected signal as the first period changed signal, and
the second selection circuit comprises:
a second signal selection circuit for multiplexing the second set of n divided frequency signals and selecting one of the n divided frequencies of the second set of frequency signals to provide the selected signal as the second period changed signal.
11. The DRAM device of claim 9 , further comprising:
a voltage generating circuit for detecting a voltage with which the oscillation circuit is operated and for producing a bias voltage to the oscillation circuit in response to the detected voltage, the oscillation circuit being biased with the bias voltage for performing a stable oscillation operation.
12. The DRAM device of claim 11 , further comprising:
a process variation responding circuit for responding to the process variation and providing a response signal to the voltage generating circuit, so as to provide a response voltage to the oscillation circuit, so that the oscillation circuit varies its oscillation frequency in accordance with the response voltage.
13. The DRAM device of claim 7 , wherein:
the process variation provider comprises:
a code provider for providing a variation code representing 2 i , i being the designated first parameter of a positive or negative integer, the first frequency dividing circuit dividing the oscillation frequency by 2 i , and
the temperature change provider comprises:
another code provider for providing a temperature change code representing 2 j , j being the designated second parameter, j being a positive or negative integer, the second frequency dividing circuit dividing the frequency of the first period changed signal by 2 j .
14. The DRAM device of claim 9 , further comprising:
a predetermined time setting circuit for responding to the process variation code and the temperature change code and for providing a setting signal in a case when the process variation code and the temperature change code are predetermined specific codes, the setting signal setting a predetermined refresh time.
15. The DRAM device of claim 9 , wherein:
the first decoder comprises:
a decoding circuit for decoding the plurality of variations to provide a three-bit process variation code, and
the second decoder comprises:
another decoding circuit for decoding the plurality of temperature changes to provide a two-bi temperature change code.
16. The DRAM device of claim 6 , wherein:
the first refresh time change factor provider comprises:
a temperature change provider for providing a temperature change code for designating the first parameter, the temperature change code being derived from temperature changes comprising temperature sensed from the DRAM device, and
the second refresh time change factor provider comprises:
a process variation provider for providing a process variation code for designating the second parameter, the process variation code being derived from the process variations comprising DRAM characteristics.
17. The DRAM device of claim 16 , wherein:
the temperature change provider comprises:
a first generator for generating the temperature change code representing a plurality of temperature changes of sensed temperature variations, and
the process variation provider comprises:
a second generator for generating the process variation code representing a plurality of variations of the DRAM characteristics.
18. The DRAM device of claim 17 , wherein:
the first generator comprises:
a first decoding circuit for decoding the plurality of temperature changes and providing the temperature change code, and
the second generator comprises:
a second decoding circuit for decoding the plurality of variations and providing the process variation code.
19. The DRAM device of claim 3 , wherein:
the first frequency producing circuit comprises:
a first frequency multiplying circuit for multiplying the oscillation frequency in accordance with a first parameter to produce the first set of m frequency signals, so that the first selection circuit selects one signal of the m multiplied different frequency signals, and
the second frequency producing circuit comprises:
a second frequency multiplying circuit for multiplying the frequency of the first period changed signal in accordance with a second parameter to produce the second set of n frequency signals, so that the second selection circuit selects one signal of the n multiplied different frequency signals.
20. A method for self-refreshing a dynamic random access memory (DRAM) device having an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column, the DRAM device being operable in a self-refresh mode, the method comprising:
providing a self-refresh mode signal that is enabled in the self-refresh mode;
producing an oscillation signal in response to the self-refresh mode signal to provide a basic time period;
changing the basic time period in response to one of two refresh time change factors, the time change factors including a process variation factor relating to the DRAM device and a temperature change factor relating to the DRAM device to provide a changed time period; and
further changing the changed time period in response to the other refresh time change factor, to provide a further changed time period for self-refreshing.
21. The method of claim 20 , wherein the step of changing comprises:
changing the repetition period of the oscillation signal in accordance with the one refresh time change factor to provide a first period changed signal having the changed time period.
22. The method of claim 21 , wherein the step of further changing comprises:
changing the repetition period of the first period changed signal in accordance with the other refresh time change factor to provide a second period changed signal having the further changed time period.
23. The method of claim 22 , wherein the step of changing the repetition period of the oscillation signal comprises:
dividing the oscillation frequency in accordance with a first parameter to produce a first set of m frequency signals having m divided frequencies.
24. The method of claim 23 , further comprising:
selecting one of the first set of m frequency signals to provide the selected signal as the first period changed signal.
25. The method of claim 24 , wherein the step of changing the repetition period of the first period changed signal comprises:
dividing the frequency of the first period changed signal in accordance with a second parameter to produce a second set of n frequency signals having n divided frequencies.
26. The method of claim 25 , further comprising:
selecting one of the second set of n frequency signals to provide the selected signal as the second period changed signal.
27. The method of claim 25 , further comprising:
providing a process variation code derived from the DRAM characteristics; and
providing a temperature change code derived from temperature sensed from the DRAM device.
28. The method of claim 22 , wherein the step of changing the repetition period of the oscillation signal comprises:
multiplying the oscillation frequency in accordance with a first parameter to produce a first set of m frequency signals having m multiplied frequencies.
29. The method of claim 24 , wherein the step of changing the repetition period of the first period changed signal comprises:
multiplying the frequency of the first period changed signal in accordance with a second parameter to produce a second set of n frequency signals having n multiplied frequencies.
30. A self-refresh controller for use in a dynamic random access memory (DRAM) device selectively operable in a self-refresh mode and a non self-refresh mode, the DRAM device having an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column, the self-refresh controller comprising:
a mode detection circuit for detecting an entry into and an exit from the self-refresh mode to provide a self-refresh mode signal;
an oscillation circuit for producing an oscillation signal in response to the self-refresh mode signal to provide a basic time period; and
a refresh time change circuit for changing the basic time period in response to one of two refresh time change factors of process variations relating to the DRAM device and temperature changes relating to the DRAM device to provide a changed time period and further changing the changed time period in response to the other refresh time change factor, to provide a further changed time period for self-refreshing.