Data mirroring in serial-connected memory system
View Patent ↗A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.
1. A method of data mirroring between a first and a second memory device in a serial-connected memory system, the method comprising:
providing a bypass command to the first memory device;
providing a write data packet to the first and second memory devices, wherein the write data packet is passed to the second memory device through the first memory device; and
providing a write data packet command to the first and second memory devices,
wherein the bypass command includes:
a mode register set command for setting a bypass mode of the first memory device;
a first burst data load command for setting a column address of the first memory device; and
a second burst data load command for setting a column address of the second memory device,
thereby mirroring the write data packet between the first and second memory devices.
2. The method as claimed in claim 1 , wherein providing the bypass command to the first memory device comprises enabling a bypass function of the first memory device.
3. The method as claimed in claim 1 , wherein providing the write data packet to the first and second memory devices comprises:
providing a receive start command to the first memory device; and
providing a receive start command to the second device.
4. The method as claimed in claim 1 , wherein providing the write data packet to the first and second memory devices comprises:
receiving the write data packet in the first memory device;
bypassing the write data packet through the first memory device; and
receiving the write data packet in the second memory device.
5. The method as claimed in claim 4 , wherein receiving the write data packet in the first memory device comprises loading the write data packet into a page buffer within the first memory device.
6. The method as claimed in claim 4 , wherein receiving the write data packet in the second memory device comprises loading the write data packet into a page buffer within the second memory device.
7. The method as claimed in claim 1 , wherein providing a write data packet command to the first and second memory devices comprises:
providing a first page program command to the first memory device; and
providing a second page program command to the second memory device.
8. The method as claimed in claim 7 , further comprising:
checking a status of the first page program command; and
checking a status of the second page program command.
9. The method as claimed in claim 2 , further comprising disabling the bypass function of the first memory device.
10. The method as claimed in claim 1 , wherein providing a write data packet comprises generating an error correction code (ECC) from data within a data field within the write data packet and storing the ECC in a spare field within the write data packet.
11. A memory system comprising:
a plurality of serial-connected memory devices, including a first memory device and a second memory device, and
a memory controller for:
providing a bypass command to the first memory device;
providing a write data packet to the first memory device and bypassing the write data packet to the second memory device, wherein the write data packet is passed to the second memory device through the first memory device; and
providing a write command to the first and second memory devices for mirroring the write data packet written in the first second memory device in the second memory device,
wherein the bypass command comprises:
a mode register set command for setting a bypass mode of the first memory device;
a first burst data load command for setting a column address of the first memory device; and
a second burst data load command for setting a column address of the second memory device.
12. The memory system as claimed in claim 11 , wherein the plurality of serial-connected memory devices and the memory controller comprise a daisy-chain topology.
13. The memory system as claimed in claim 11 , wherein the plurality of serial-connected memory devices and the memory controller comprise a ring topology.
14. A memory system comprising:
a plurality of serial-connected memory devices, including a first memory device and a second memory device, and
a memory controller for:
providing a bypass, command to the first memory device;
providing a write data packet to the first memory device and bypassing the write data packet to the second memory device, wherein the write data packet is passed to the second memory device through the first memory device; and
providing a write command to the first and second memory devices for mirroring the write data packet written in the first second memory device in the second memory device,
wherein each of the serial-connected memory devices comprises:
a first link for inputting one or more packets into the memory device;
a first input for inputting a command strobe signal into the memory device, the command strobe signal for delineating a first packet input into the memory device by the first data link, the first packet containing a command for executing by the memory device;
a second input for inputting a data strobe signal into the memory device, the data strobe signal for delineating a second packet input into the memory device by the first data link, the second packet containing data for storing in the memory device;
a first output for outputting the command strobe signal from the memory device;
a second output for outputting the data strobe signal from the memory device; and
a second link for:
outputting the first packet from the memory device while the command strobe signal is output from the memory device at the output, and
outputting the second packet from the memory device while the data strobe signal is output from the memory device at the output.
15. The memory system as claimed in claim 11 , wherein the first and second memory devices each comprise a page buffer for receiving the write data packet.
16. The memory system as claimed in claim 11 , wherein the write command comprises:
a first page program command for setting a row address of the first memory device; and
a second page program command for setting a row address of the second memory device.
17. The memory system as claimed in claim 11 , wherein providing a write data packet comprises generating an error correction code (ECC) from data within a data field within the write data packet and storing the ECC in a spare field within the write data packet.
18. A solid-state disk drive comprising:
a plurality of serial-connected memory devices, including a first memory device and a second memory device, and
a memory controller for:
providing a bypass command to the first memory device;
providing a write data packet to the first memory device and bypassing the write data packet to the second memory device, wherein the write data packet is passed to the second memory device through the first memory device; and
providing a write command to the first and second memory devices for mirroring the write data packet written in the first second memory device in the second memory device,
wherein the bypass command includes:
a mode register set command for setting a bypass mode of the first memory device;
a first burst data load command for setting a column address of the first memory device; and
a second burst data load command for setting a column address of the second memory device.
19. The solid-state disk drive as claimed in claim 18 , wherein the memory controller further comprises means for providing an interface between the plurality of serial-connected memory devices and an external apparatus.
20. The solid-state disk drive as claimed in claim 19 , wherein a type of the interface is chosen from a list consisting of: USB (Universal Serial Bus), SD (Secure Digital), CF (Compact Flash), and AHCI (Advanced Host Controller Interface).
21. The solid-state disk drive as claimed in claim 19 , wherein a format of the solid-state disk drive is chosen from a list consisting of: FAT (File Allocation Table), NTFS (New Technology File System), JFFS (Journaling Flash File System), YAFFS (Yet Another Flash File System), and ZFS (Zettabyte File System).
22. A method of reading in a serial-connected memory system having at least a first memory device including data within a first data field within a first page and a first error correction code (ECC) within a first spare field within the first page; a second memory device including data within a second data field within a second page and a second ECC within a second spare field within the second page; and wherein the data within the second data field is a mirrored version of the data within the first data field, the method comprising:
reading the first page from the first memory device;
generating a third ECC from the data within the first data field;
comparing the first ECC with the third ECC;
reading the second page from the second memory device;
generating a fourth ECC from the data within the second data field;
comparing the second ECC with the fourth ECC;
bitwise comparing the data from the first data field with the data from the second data field;
generating a third data field by inverting a bit of the data from the first or second data field corresponding to the bitwise comparison;
generating a fifth ECC from the third data field; and
comparing the fifth ECC with the first or second ECC.
23. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
comparing the second ECC with the third ECC.
24. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
comparing the first ECC with the fourth ECC.
25. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
comparing the third ECC with the fourth ECC.
26. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
correcting the data within the first data field using the first ECC.
27. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
correcting the data within the second data field using the second ECC.
28. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
correcting the data within the first data field using the second ECC.
29. The method of reading in a serial-connected memory system as claimed in claim 22 , further comprising:
correcting the data within the second data field using the first ECC.