Memory system having a plurality of serially connected devices
View Patent ↗A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.
1. A semiconductor memory device, comprising:
memory;
a plurality of inputs for receiving from a previous device a command latch enable signal, an address latch enable signal and an information signal;
a device identification register for storing register bits that distinguish the memory device from other possible memory devices;
circuitry for comparing identification bits in the information signal with the register bits to provide positive or negative indication as to whether the identification bits match the register bits, and if the indication is positive then the memory device is configured to respond as having been selected by a controller, and if the indication is negative then the memory device is configured to respond as having not been selected by the controller;
a plurality of outputs for releasing a set of output signals towards a next device;
control circuitry configured to interpret, when the indication is positive, the information signal based on the command latch enable signal and the address latch enable signal; and
bypass circuitry configured to transfer, when the indication is negative, the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.
2. The semiconductor memory device defined in claim 1 , wherein one of the inputs is adapted to receive a data strobe signal providing synchronous reference for data contained in the information signal.
3. The semiconductor memory device defined in claim 2 , wherein the data strobe signal is an intermittently driven timing signal.
4. The semiconductor memory device defined in claim 1 , wherein one of the outputs is adapted to transmit an echo of a data strobe signal providing synchronous reference for data contained in a subset of the set of output signals.
5. The semiconductor memory device defined in claim 4 , wherein the echo of the data strobe signal is an intermittently driven timing signal.
6. The semiconductor memory device defined in claim 1 , wherein the command latch enable signal and the address latch enable signal are capable of acquiring respective states, wherein to interpret the information signal based on the command latch enable signal and the address latch enable signal, the control circuitry is configured to interpret the information signal based on the states of the command latch enable signal and the address latch enable signal.
7. The semiconductor memory device defined in claim 1 , wherein to interpret the information signal based on the command latch enable signal and the address latch enable signal, the control circuitry is configured to interpret the information signal as conveying command information when the command latch enable signal is asserted and the address latch enable signal is de-asserted.
8. The semiconductor memory device defined in claim 1 , wherein to interpret the information signal based on the command latch enable signal and the address latch enable signal, the control circuitry is configured to interpret the information signal as conveying address information when the command latch enable signal is de-asserted and the address latch enable signal is asserted.
9. The semiconductor memory device defined in claim 8 , wherein the memory comprises an array of memory cells arranged in addressable pages.
10. The semiconductor memory device defined in claim 9 , wherein the address information specifies at least part of an address of one of the pages in the memory.
11. The semiconductor memory device defined in claim 1 , wherein to interpret the information signal based on the command latch enable signal and the address latch enable signal, the control circuitry is configured to interpret the information signal as conveying data information when, after a command to program data into the memory has been received by the memory device, the command latch enable signal is asserted and the address latch enable signal is also asserted.
12. The semiconductor memory device defined in claim 1 , wherein the control circuitry is further configured to place retrieved data onto a subset of the outputs when, after a command to read data from the memory has been received by the memory device, an echo of the command latch enable signal is asserted and an echo of the address latch enable signal is also asserted.
13. The semiconductor memory device defined in claim 12 , wherein the retrieved data is retrieved from the memory in response to receipt of the command to read data.
14. The semiconductor memory device defined in claim 1 , further comprising an input for receiving a mode signal indicative of whether the device has been placed in a read mode or a write mode by the controller.
15. The semiconductor memory device defined in claim 14 , wherein to interpret the information signal based on the command latch enable signal and the address latch enable signal, the control circuitry is configured to interpret the information signal as conveying data information when the command latch enable signal is asserted and the address latch enable signal is also asserted while the mode signal is indicative of the device having been placed in write mode by the controller.
16. The semiconductor memory device defined in claim 14 , wherein the control circuitry is further configured to place retrieved data onto a subset of the outputs in response to the command latch enable signal being asserted and the address latch enable signal also being asserted while the mode signal is indicative of the device having been placed in read mode by the controller.
17. The semiconductor memory device defined in claim 16 , wherein the retrieved data is retrieved from the memory in response to receipt of the command to read data.
18. The semiconductor memory device defined in claim 1 , further comprising an input for receiving the device-external clock signal from the controller.
19. The semiconductor memory device defined in claim 18 , wherein the device-external clock signal is received from the controller over a dedicated signal line connecting the device to the controller without passing through any other semiconductor memory device.
20. The semiconductor memory device defined in claim 18 , wherein the device-external clock signal is received from the controller via the previous device.
21. The semiconductor memory device defined in claim 20 , further comprising releasing the device-internal clock signal to the next device via one of the outputs.
22. The semiconductor memory device defined in claim 18 , further comprising a clock recovery circuit to derive the device-internal clock signal from the device-external clock signal.
23. The semiconductor memory device defined in claim 22 , wherein the clock recovery circuit comprises circuit components in a feedback loop configuration.
24. The semiconductor memory device defined in claim 23 , wherein the clock recovery circuit comprises a delay locked loop or a phase locked loop.
25. A method, comprising:
storing register bits in a memory device, the register bits distinguishing the memory device from other possible memory devices;
receiving a command latch enable signal, an address latch enable signal and an information signal at a memory device;
comparing identification bits in the information signal with the register bits to provide positive or negative indication as to whether the identification bits match the register bits, and the indication being positive when the memory device has been selected by a controller, and the indication being negative when the memory device has not been selected by the controller;
interpreting, when the indication is positive, the information signal based on the command latch enable signal and the address latch enable signal; and
transferring, when the indication is negative, the command latch enable signal, the address latch enable signal and the information signal to a neighboring device.
26. The method defined in claim 25 , further comprising receiving a data strobe signal at the memory device, the data strobe signal for providing synchronous reference for data contained in the information signal.
27. The method defined in claim 26 , wherein the data strobe signal is an intermittently driven timing signal.
28. The method defined in claim 25 , further comprising transmitting an echo of a data strobe signal from the memory device, the echo of the data strobe signal for providing synchronous reference for data outputted from the memory device.
29. The method defined in claim 28 , wherein the echo of the data strobe signal is an intermittently driven timing signal.
30. The method defined in claim 25 , wherein the command latch enable signal and the address latch enable signal are capable of acquiring respective states, wherein interpreting the information signal based on the command latch enable signal and the address latch enable signal comprises interpreting the information signal based on the states of the command latch enable signal and the address latch enable signal.
31. The method defined in claim 25 , wherein interpreting the information signal based on the command latch enable signal and the address latch enable signal comprises interpreting the information signal as conveying command information when the command latch enable signal is asserted and the address latch enable signal is de-asserted.
32. The method defined in claim 25 , wherein interpreting the information signal based on the command latch enable signal and the address latch enable signal comprises interpreting the information signal as conveying address information when the command latch enable signal is de-asserted and the address latch enable signal is asserted.
33. The method defined in claim 25 , interpreting the information signal based on the command latch enable signal and the address latch enable signal comprises interpreting the information signal as conveying data information when, after a command to program data into memory has been received by the memory device, the command latch enable signal is asserted and the address latch enable signal is also asserted.
34. The method defined in claim 25 , further comprising retrieving data from memory in response to receipt of a command to read data.
35. The method defined in claim 34 , further comprising placing the data retrieved from memory onto a set of outputs in response to the command latch enable signal being asserted and the address latch enable signal also being asserted after receipt of the command to read data.
36. The method defined in claim 25 , further comprising receiving a mode signal indicative of whether the device has been placed in a read mode or a write mode by the controller, wherein interpreting the information signal based on the command latch enable signal and the address latch enable signal comprises interpreting the information signal as conveying data information when the command latch enable signal is asserted and the address latch enable signal is also asserted while the mode signal is indicative of the memory device having been placed in write mode by the controller.