Circuit and method for testing multi-device systems
View Patent ↗A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.
1. A memory device comprising:
a memory array having cells for storing data;
test circuitry for detecting a defective cell in the memory array and providing a local defect signal when the defective cell is detected, the test circuitry combining the local defect signal with a global defect signal to provide an updated global defect signal; and
output path circuitry for providing the global defect signal to the test circuitry and for outputting the updated global defect signal.
2. The memory device of claim 1 , wherein
the memory array includes a first memory bank and a second memory bank, and
the test circuitry is configured to compare cell data from the first memory bank to cell data of the second memory bank.
3. The memory device of claim 1 , wherein all the cells of the memory array are written to store an identical logic state.
4. The memory device of claim 1 , wherein the test circuitry is configured to determine mismatching contents between pairs of cells of the memory array, thereby indicating that at least one of the pairs of cells is the defective cell.
5. The memory device of claim 1 , wherein the test circuitry is configured for determining mismatching contents between N pairs of cells of the memory array at the same time, where N is an integer number, the test circuitry providing N local defect signals each corresponding to one of the N pairs of cells.
6. The memory device of claim 5 , wherein the output path circuitry includes a register for storing the N local defect signals.
7. The memory device of claim 6 , wherein the register includes a parallel to serial register for receiving the N local defect signals in parallel, the parallel to serial register being configured to provide each of the N local defect signals serially in response to a clock signal.
8. The memory device of claim 1 , wherein the test circuitry includes logic circuitry for comparing contents of a first memory cell of the memory array to a second memory cell of the memory array, the local defect signal being provided when the contents of the first memory cell and the second memory cell mismatch.
9. The memory device of claim 8 , wherein the logic circuitry includes exclusive OR logic having a first input for receiving the first memory cell content and a second input for receiving the second memory cell content.
10. The memory device of claim 1 , wherein the test circuitry includes a compression circuit for providing the updated global defect signal in response to the local defect signal and the global defect signal, the updated global defect signal corresponding to a detected defect if at least one of the updated global defect signal and the local defect signal corresponds respectively to a detected defect.
11. The memory device of claim 10 , wherein the compression circuit includes OR logic having a first input for receiving the global defect signal and a second input for receiving the local defect signal.
12. The memory device of claim 10 , wherein the compression circuit receives the global defect signal from the output path circuitry, the global defect signal being provided by another memory device.
13. The memory device of claim 1 , wherein the test circuitry includes a path selector for selectively providing one of read data and the updated global defect signal to an output terminal.
14. The memory device of claim 13 , wherein the path selector provides as the read data external read data provided by another memory device, or local read data provided by the memory array.
15. The memory device of claim 14 , wherein the output path circuitry includes an input terminal for receiving one of the external read data and the global defect signal.
16. The memory device of claim 14 , wherein the output path circuitry includes a device selector for selectively passing one of the external read data and the local read data.