STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES
Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin.
1 . A system comprising:
a plurality of devices, each of the plurality of devices including a status input pin, a status output pin, and separate data input and output pins, and the plurality of devices including:
a) a plurality of semiconductor memory devices including at least first and last memory devices; and
b) a controller device for communicating with the semiconductor memory devices, and
the first memory device having a status input pin connected to a status output pin of the controller device, a status output pin of the first memory device being connected to a status input pin of either an intervening memory device or the last memory device, the status input pin of the last memory device being connected to a status output pin of either another intervening memory device, the intervening memory device or the first memory device, and a status output pin of the last memory device being connected to a status input pin of the controller device so that a status ring is formed, and each of the plurality of devices being on the status ring, and the status ring providing a status communications path that is independent of any data communications path between any of the semiconductor memory devices and the controller device.
2 . The system of claim L wherein at least one of the semiconductor memory devices is configured to output a status packet onto the status ring to provide indication of a status change within the at least one of the semiconductor memory devices.
3 . The system of claim 2 , wherein the status packet includes identification bits for identifying that the status packet originated from the at least one of the semiconductor memory devices.
4 . The system of claim 1 , wherein at least one of the semiconductor memory devices is configured to output a single strobe pulse onto the status ring to provide indication of a status change within the at least one of the semiconductor memory devices.
5 . The system of claim 1 , wherein at least one of the semiconductor memory devices includes at least one data output pin for outputting data in synchronous relation to edges of a clock signal.
6 . The system of claim 5 , further comprising at least two asynchronous flash memory devices, the asynchronous flash memory devices being connected to the at least one of the semiconductor memory devices, and wherein the at least one of the semiconductor memory devices is a bridge device that is configured to communicate asynchronously with either of the at least two asynchronous flash memory devices.
7 . The system of claim 6 , wherein the at least one of the semiconductor memory devices is configured to output a status packet onto the status ring to provide indication of a status change within the at least one of the semiconductor memory devices.
8 . The system of claim 7 , wherein the status packet include identification bits for identifying that the status packet originated from the at least one of the semiconductor memory devices.
9 . The system of claim 6 , wherein the at least one of the semiconductor memory devices is configured to output a single strobe pulse onto the status ring to provide indication of a status change within the at least one of the memory devices.
10 . The system of claim 1 , wherein the plurality of semiconductor memory devices are flash memory devices.
11 . The system of claim 1 , wherein the flash memory devices are NAND flash memory devices.
12 . A memory device comprising:
a plurality of data pins for connection to a data bus;
a status pin for connection to a status line that is independent from the data bus;
first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration, and the strobe pulse providing an indication of the completion of the memory operation; and
second circuitry for outputting the strobe pulse onto the status line via the status pin.
13 . The memory device of claim 12 , wherein the memory device is a bridge device configured for connection to a plurality of discrete memory devices.
14 . The memory device of claim 13 , wherein the memory operation is a memory operation in one of the discrete memory devices.
15 . The memory device of claim 14 , wherein the plurality of discrete memory devices are flash memory devices, and the memory operation consists of one of program, read and erase.
16 . The memory device of claim 15 , wherein the flash memory devices are NAND flash memory devices.
17 . The memory device of claim 13 , wherein the bridge device is configured to communicate with both: i) a controller device in a ring-type topology system; and ii) the plurality of discrete memory devices in a multi-drop subsystem.
18 . A method comprising:
providing a flash memory device comprising a plurality of data pins and a status pin, the plurality of data pins connected to a data bus, and the status pin connected to a status line that is independent from the data bus;
carrying out, within the flash memory device, a memory operation having a first duration;
generating, upon completion of the memory operation, a strobe pulse of a second duration much shorter than the first duration, and the strobe pulse providing an indication of the completion of the memory operation; and
outputting the strobe pulse onto the status line via the status pin.
19 . The method of claim 18 , wherein the memory operation consists of one of program, read and erase.
20 . The method of claim 18 , wherein the flash memory device is a NAND flash memory device.
21 . A memory device comprising:
at least one data input pin;
at least one data output pin;
a status input pin configured for connection to a status output pin of either another memory device or a controller device; and
a status output pin configured for connection to a status input pin of either yet another memory device or the controller device, and
wherein the status input pin of the memory device, the status output pin of the memory device, the at least one data input pin and the at least one data output pin are each physically distinct pins from one another.
22 . The memory device of claim 21 , wherein the memory device is a flash memory device configured to carry out, within the flash memory device, a memory operation having a first duration.
23 . The memory device of claim 22 , wherein the flash memory device is further configured to generate, upon completion of the memory operation, a strobe pulse of a second duration much shorter than the first duration, and the strobe pulse providing an indication of the completion of the memory operation.
24 . The memory device of claim 23 , wherein the flash memory device is further configured to output the strobe pulse via the status output pin.
25 . The memory device of claim 22 , wherein the memory operation consists of one of program, read and erase.
26 . The memory device of claim 21 , wherein the memory device is a bridge device configured for connection to a plurality of discrete memory devices, and the bridge device is configured to communicate with both: i) the controller device in a ring-type topology system; and ii) the plurality of discrete memory devices in a multi-drop subsystem.