Method and apparatus for connecting memory dies to form a memory system
View Patent ↗A method, system and apparatus for connecting multiple memory device dies 51 - 54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52 - 54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop.
1. A memory system comprising:
a substrate having a first side and a second side;
first memory devices mounted to the first side of said substrate, and;
second memory devices mounted to the second side of said substrate in staggered formation relative to said first memory devices; and,
vias extending from the first side to the second side of the substrate and connected to connections of the first memory devices and the second memory devices.
2. The memory system as in claim 1 , wherein there are four memory devices connected in series.
3. The memory system as in claim 1 , further comprising a controller mounted to one side of said substrate configured to control operation of the first memory devices and the second memory devices.
4. A method for constructing a memory system comprising:
mounting first memory devices to a first side of a substrate to connect connections of the first memory devices to vias extending from the first side to a second side of the substrate; and,
mounting second memory devices on the second side of the substrate staggered and in opposite orientation to the first memory devices on the first side of the substrate, to connect connections of the second devices to the vias.
5. A memory system comprising:
a substrate;
first memory devices mounted to a first side of said substrate;
second memory devices mounted to a second side of said substrate and staggered from said first memory devices;
vias extending from the first side to the second side of the substrate and connected to connections of the first memory devices and the second memory devices; and
a controller connected to said substrate for controlling operation of the first memory devices and the second memory devices.
6. The memory system as in claim 5 , wherein the first memory devices and the second memory devices are serially connected to each other.
7. The memory system as in claim 6 , wherein said controller is connected to a first memory device and a last memory device of the serially connected first memory devices and second memory devices.