Data flow control in multiple independent port
View Patent ↗A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
1. A method of generating a locally generated serial output signal, the method comprising:
to generate an output from core memory:
receiving an output enable signal and a clock signal and generating a shifted clock and latch signal;
latching a locally generated parallel signal into a parallel-to-serial register using the latch signal and outputting contents of the parallel-to-serial register using the shifted clock;
to generate an output from a local register;
receiving an output enable signal and a clock signal and generating a shifted clock and latch signal; and
latching an output of the local register into a parallel-to-serial register using the latch signal and outputting contents of the parallel-to-serial register using the shifted clock.
2. The method of claim 1 wherein:
the local register comprises a status register and an ID register;
latching an output of a local register into a parallel-to-serial register using the latch signal and outputting contents of the parallel-to-serial register using the shifted clock comprises:
a) latching an output of the status register upon receipt of a command requesting a status update;
b) latching an output of the ID register upon receipt of a command requesting ID;
and wherein the output from core memory is generated unless there has been receipt of a command requesting a status update or a command requesting ID in which case the output from one of the registers is generated.
3. An apparatus for generating a locally generated serial output signal, the apparatus comprising:
a serial output controller for receiving an output enable signal and a clock signal and generates a shifted clock and latch signal;
a first parallel-to-serial register for latching a locally generated parallel signal using the latch signal and outputs contents using the shifted clock;
a second parallel-to-serial register for latching an output from a local register using the latch signal and outputs contents using the shifted clock;
a first selector for selecting between outputting the output of the first parallel-to-serial register and the second parallel-to-serial register.
4. The apparatus of claim 3 further comprising:
a second selector for selecting between a plurality of local registers as said output from a local register as a function of a received command.
5. The apparatus of claim 4 wherein the plurality of local registers comprise:
a status register that is selected by the selector when the received command is a status request command;
an ID register that is selected by the selector when the received command is an ID command;
the apparatus outputting the output from the core memory unless a status request command or an ID command has been received.
6. The apparatus of claim 4 further comprising:
a serial output controller for receiving an output enable signal and a clock signal and generates a shifted clock and latch signal;
a first register for latching a locally generated parallel signal using the latch signal and outputs contents using the shifted clock;
a second register for latching an output from a local register using the latch signal and outputs contents using the shifted clock; and
a selector for selecting between outputting the output of the first parallel-to-serial register and the second parallel-to-serial register.