Single-strobe operation of memory devices
View Patent ↗An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
1. A memory device comprising:
at least one pin configured to receive a packet including a bit set to a first logic level or a second logic level;
a strobe input configured to receive a single strobe signal, the single strobe signal for delimiting the packet; and
strobe generator circuitry configured to:
i) employ the single strobe signal to generate a corresponding command strobe signal when the bit is set to the first logic level; and
ii) employ the single strobe signal to generate a corresponding data strobe signal when the bit is set to the second logic level.
2. The memory device of claim 1 wherein the packet includes a packet header followed by a payload, and the packet header includes the bit set to the first logic level or the second logic level.
3. The memory device of claim 1 wherein the first logic level is “1” and the second logic level is “0”.
4. The memory device of claim 1 wherein the packet includes a packet header and a secondary packet.
5. The memory device of claim 4 wherein the command strobe signal delimits the secondary packet when the bit is set to the first logic level.
6. The memory device of claim 4 wherein the data strobe signal delimits the secondary packet when the bit is set to the second logic level.
7. The memory device of claim 1 wherein the at least one pin is a data bus pin.
8. The memory device of claim 1 wherein the at least one pin is eight pins.
9. A method comprising:
providing a single strobe signal as input to a device, the single strobe signal delimiting a packet received on an at least one pin of the device;
identifying whether a predetermined bit of the packet has been set to a first logic level or a second logic level;
if the predetermined bit of the packet has been set to the first logic level, employing the single strobe signal to generate a corresponding command strobe signal; and
if the predetermined bit of the packet has been set to the second logic level, employing the single strobe signal to generate a corresponding data strobe signal.
10. The method of claim 9 wherein the first logic level is “1” and the second logic level is “0”.
11. The method of claim 9 wherein the packet includes a packet header and a secondary packet.
12. The method of claim 11 wherein the command strobe signal delimits the secondary packet if the predetermined bit of the packet has been set to the first logic level.
13. The method of claim 11 wherein the data strobe signal delimits the secondary packet if the predetermined bit of the packet has been set to the second logic level.
14. The method of claim 9 wherein the device is a memory device.
15. A method of controlling a memory device, said method comprising:
transmitting a strobe signal delimiting a primary packet; and
concurrently transmitting said primary packet on a data bus, said primary packet including a packet header followed by a payload, said packet header indicating a type to be associated with said payload.
16. The method of claim 15 wherein said payload is a secondary packet.
17. The method of claim 16 wherein said type to be associated with said secondary packet is Command and Write Data Packet.
18. The method of claim 16 wherein said type to be associated with said secondary packet is Read Data Packet.
19. A memory device controller comprising:
a strobe output for transmitting a strobe signal delimiting a primary packet; and
a plurality of data bus outputs for transmitting said primary packet on a data bus, said primary packet including a packet header followed by a payload, said packet header indicating a type to be associated with said payload.
20. The memory device controller of claim 19 wherein the memory device controller is a double-data-rate synchronous memory device controller.
21. The method of claim 15 wherein the data bus facilitates communication of read data.
22. The memory device controller of claim 19 wherein the data bus is configured to facilitate communication of read data to the memory controller device.