PLL locking control in daisy chained memory system
View Patent ↗A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller.
1. A memory module for use in a daisy chained memory system having multiple memory modules each module including a Phase Locked Loop (PLL) comprising:
circuitry configured to monitor the status of the PLL of a backward device in a daisy chain;
further circuitry configured to delay locking of said PLL until locking has occurred in the backward device;
locking circuitry configured to lock the PLL upon notification from said further circuitry; and
a locking status pin, the locking status pin being a Q< 0 > pin.
2. A memory system comprising:
a plurality of memory modules connected in series each memory module including a Phase Locked Loop;
a memory controller connected to the first and last memory module;
circuitry in each memory module configured to monitor the status of the PLL of an adjacent backward device in the daisy chain;
further in each memory module, circuitry configured to delay locking of said PLL until locking has occurred in the adjacent backward device;
locking circuitry in each memory module configured to lock the PLL upon notification from said further circuitry;
a locking status pin on each memory module, the locking status pin being a Q< 0 > pin.
3. A memory system comprising:
a plurality of memory modules connected in series each memory module including a Phase Locked Loop;
a memory controller connected to the first and last memory module;
circuitry in each memory module configured to monitor the status of the PLL of an adjacent backward device in the daisy chain;
further in each memory module, circuitry configured to delay locking of said PLL until locking has occurred in the adjacent backward device;
locking circuitry in each memory module configured to lock the PLL upon notification from said further circuitry;
a locking status pin on each memory module, the locking status pin being an added dedicated pin.
4. A memory system comprising:
a plurality of memory modules connected in series each memory module including a Phase Locked Loop;
a memory controller connected to the first and last memory module;
circuitry in each memory module configured to monitor the status of the PLL of an adjacent backward device in the daisy chain;
further in each memory module, circuitry configured to delay locking of said PLL until locking has occurred in the adjacent backward device;
locking circuitry in each memory module configured to lock the PLL upon notification from said further circuitry;
a locking status pin on each memory module;
a PLL re-locking register configured to store PLL information of the state of the PLL locking state; and,
a flag generator configured to generate an asynchronous wait flag.