Granted Patent B2

US 10,236,032 · App. 12/212,902 · Granted Mar 19, 2019

Abstract

Claims (49)

1. A mass data storage system, comprising:

a memory controller for issuing and receiving signals to carry out memory operations;

a motherboard comprising at least two socket connectors serially connected to each other and each configured to provide electrical continuity of signal pathways for establishing a serially connected ring from the memory controller via each of the at least two socket connectors and back to the memory controller when empty, each of the at least two socket connectors including:

a plurality of first electrical pins positioned in opposing respective alignment with a plurality of second electrical pins, wherein the first electrical pins contact with the second electrical pins when no memory module is inserted; and

at least one non-volatile memory module comprising:

a dual-faced connector comprising a plurality of first electrical conductors disposed on a first face of the connector and a plurality of second electrical conductors disposed on a second face of the connector, the plurality of first and second electrical conductors electrically connected to a chain of serially connected non-volatile memory devices, wherein the chain of serially connected non-volatile memory devices includes:

a first non-volatile memory device having inputs coupled to the first electrical conductors for receiving the signals issued by the memory controller and having outputs for providing the signals, and

a last non-volatile memory device having inputs for receiving the signals from the first non-volatile memory device and having outputs coupled to the second electrical conductors for providing the signals;

wherein mating of the dual-faced connector with a given one of the at least two socket connectors physically separates the plurality of first electrical pins from the plurality of second electrical pins and causes the plurality of first electrical conductors to contact the plurality of first electrical pins and the plurality of second electrical conductors to contact the plurality of second electrical pins, thereby causing the chain of serially connected non-volatile memory devices to be inserted into the ring, thereby to allow the memory controller to carry out the memory operations on the non-volatile memory devices in the chain; and

wherein the memory controller issues signals to said first electrical pins of a first of the at least two socket connectors and receives signals from said second electrical pins of a last of the at least two socket connectors for carrying out memory operations.

2. The mass data storage system defined in claim 1 , wherein the motherboard comprises at least one additional socket connector and provides signal pathways for establishing a second ring from the memory controller via each of the at least one additional socket connector and back to the memory controller.

3. The mass data storage system defined in claim 2 , wherein mating of the dual-faced connector with a given one of the at least one additional socket connector causes the chain of serially connected non-volatile memory devices to be inserted into the second ring, thereby to allow the memory controller to carry out the memory operations on the serially connected non-volatile memory devices in the chain.

4. The mass data storage system defined in claim 1 , wherein a particular one of the at least one non-volatile memory module is an expansion module comprising a connection portion and a memory portion attachable to and detachable from the connection portion, the memory portion comprising the chain of serially connected non-volatile memory devices of the particular one of the at least one non-volatile memory module, the connection portion comprising the dual-faced connector of the particular one of the at least one non-volatile memory module.

5. The mass data storage system defined in claim 4 , wherein the memory portion comprises at least one memory sub-module, and wherein the chain of serially connected non-volatile memory devices of the particular one of the at least one non-volatile memory module is distributed over the at least one memory sub-module.

6. The mass data storage system defined in claim 5 , wherein the at least one memory sub-module comprises a plurality of memory sub-modules.

7. The mass data storage system defined in claim 6 , wherein each of the memory sub-modules is independently matable with the expansion portion.

8. The mass data storage system defined in claim 1 , wherein the dual-faced connector and the given one of the at least two socket connectors are configured to provide rigid support for said non-volatile memory module when said mating occurs.

9. The mass data storage system defined in claim 1 , wherein the memory controller is configured to carry out the memory operations based on instructions received from a memory control hub that interfaces with a processing unit.

10. The mass data storage system defined in claim 1 , wherein the memory controller is mounted on the motherboard.

11. A computing device comprising:

an input/output interface;

a main memory storing instructions;

at least one processor for executing computing operations based on instructions stored in the main memory; and

a mass data storage system electrically connected to the at least one processor, the mass data storage system comprising:

a memory controller for issuing and receiving signals to carry out memory operations based on signals received from the at least one processor;

a motherboard comprising at least two socket connectors serially connected to each other and each configured to provide electrical continuity of signal pathways for establishing a serially connected ring from the memory controller via each of the at least two socket connectors and back to the memory controller when empty, each of the at least two socket connectors including:

a plurality of first electrical pins positioned in opposing respective alignment with a plurality of second electrical pins, wherein the first electrical pins contact with the second electrical pins when no memory module is inserted; and

at least one non-volatile memory module comprising:

a dual-faced connector comprising a plurality of first electrical conductors disposed on a first face of the connector and a plurality of second electrical conductors disposed on a second face of the connector, the plurality of first and second electrical conductors electrically connected to a chain of serially connected non-volatile memory devices, wherein the chain of serially connected non-volatile memory devices includes:

a first non-volatile memory device having inputs coupled to the first electrical conductors for receiving the signals issued by the memory controller and having outputs for providing the signals, and

a last non-volatile memory device having inputs for receiving the signals from the first non-volatile memory device and having outputs coupled to the second electrical conductors for providing the signals;

wherein mating of the dual-faced connector with a given one of the at least two socket connectors physically separates the plurality of first electrical pins from the plurality of second electrical pins and causes the plurality of first electrical conductors to contact the plurality of first electrical pins and the plurality of second electrical conductors to contact the plurality of second electrical pins, thereby causing the chain of serially connected non-volatile memory devices to be inserted into the ring, thereby to allow the memory controller to carry out the memory operations on the non-volatile memory devices in the chain; and

wherein the memory controller issues signals to said first electrical pins of a first of the at least two socket connectors and receives signals from said second electrical pins of a last of the at least two socket connectors for carrying out memory operations.

12. A server, comprising:

a network interface to enable communication with at least one client over a network;

a processing portion capable of executing at least one application and servicing requests received from said at least one client; and

a mass data storage system electrically connected to the processing portion, the mass data storage system comprising:

a memory controller for issuing and receiving signals to carry out memory operations based on signals received from the processing portion;

a motherboard comprising at least two socket connectors serially connected to each other and each configured to provide electrical continuity of signal pathways for establishing a serially connected ring from the memory controller via each of the at least two socket connectors and back to the memory controller when empty, each of the at least two socket connectors including:

a plurality of first electrical pins positioned in opposing respective alignment with a plurality of second electrical pins, wherein the first electrical pins contact with the second electrical pins when no memory module is inserted; and

at least one non-volatile memory module comprising:

a dual-faced connector comprising a plurality of first electrical conductors disposed on a first face of the connector and a plurality of second electrical conductors disposed on a second face of the connector, the plurality of first and second electrical conductors electrically connected to a chain of serially connected non-volatile memory devices, wherein the chain of serially connected non-volatile memory devices includes:

a first non-volatile memory device having inputs coupled to the first electrical conductors for receiving the signals issued by the memory controller and having outputs for providing the signals, and

a last non-volatile memory device having inputs for receiving the signals from the first non-volatile memory device and having outputs coupled to the second electrical conductors for providing the signals;

wherein mating of the dual-faced connector with a given one of the at least two socket connectors physically separates the plurality of first electrical pins from the plurality of second electrical pins and causes the plurality of first electrical conductors to contact the plurality of first electrical pins and the plurality of second electrical conductors to contact the plurality of second electrical pins, thereby causing the chain of serially connected non-volatile memory devices to be inserted into the ring, thereby to allow the memory controller to carry out the memory operations on the non-volatile memory devices in the chain; and

wherein the memory controller issues signals to said first electrical pins of a first of the at least two socket connectors and receives signals from said second electrical pins of a last of the at least two socket connectors for carrying out memory operations.

13. The mass data storage system defined in claim 1 , wherein the chain of serially connected non-volatile memory devices further includes at least one intervening non-volatile memory device receiving the signals from the first non-volatile memory device and providing the signals to the last non-volatile memory device.

14. The computing device defined in claim 11 , wherein the chain of serially connected non-volatile memory devices further includes at least one intervening non-volatile memory device receiving the signals from the first non-volatile memory device and providing the signals to the last non-volatile memory device.

15. The server defined in claim 12 , wherein the chain of serially connected non-volatile memory devices further includes at least one intervening non-volatile memory device receiving the signals from the first non-volatile memory device and providing the signals to the last non-volatile memory device.

Assignments (6)