Circuit and method for testing multi-device systems
View Patent ↗A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.
1. A method for testing a memory system having serially connected memory devices, the method comprising
writing test data to memory cells of each memory device;
in each memory device, testing the memory cells and producing result data corresponding to a fail status if at least one of previous result data from a previous device and local result data from testing of the memory cells corresponds to the fail status.
2. The method of claim 1 , wherein the result data, the local result data and the previous result data are single-bit signals.
3. The method of claim 1 , wherein the step of writing test data to memory cells of each memory device includes writing identical test data to all the memory cells of each memory device.
4. The method of claim 1 , wherein in each memory device, testing the memory cells includes reading the test data from at least two memory cells and comparing the read test data of the at least two memory cells to each other for detecting one memory cell defect.
5. The method of claim 4 , wherein in each memory device, testing the memory cells further includes producing the local result data corresponding to the fail status if the one memory cell defect is detected and producing the local result data corresponding to a pass status in the absence of the one memory cell defect.
6. The method of claim 4 , wherein in each memory device, testing the memory cells includes executing an exclusive OR operation upon the test data of the at least two memory cells for producing the local result data.
7. The method of claim 1 , wherein producing the result data includes receiving the previous result data from the previous device, and comparing the previous result data to the local result data.
8. The method of claim 7 , wherein comparing includes logically OR'ing the previous result data with the local result data.
9. The method of claim 8 , further comprising, in each memory device, selectively passing one of the result data and input data received at an input port to an output port.
10. The method of claim 1 , further including providing the previous result data preset to have a pass status to a first memory device of the serially connected memory devices.
11. The method of claim 1 , wherein the result data includes providing the result data to a subsequent memory device of the serially connected memory devices.
12. The method of claim 1 , wherein producing the result data includes providing the result data to test circuitry.
13. A memory system, comprising:
a test pattern provider for providing test data;
serially interconnected memory devices having memory cells, each memory device storing the test data, comparing the test data stored in the memory cells to detect a defect, and producing result data corresponding to a defect if at least one of local result data from comparing the test data stored in the memory cells and previous result data from a previous device corresponds to a defect; and
a test pattern receiver for receiving the result data.
14. The memory system of claim 10 , further comprising a memory controller which includes the test pattern provider and the test pattern receiver.
15. The memory system of claim 10 , wherein each of the serially connected memory devices includes a test circuit for comparing the test data stored in the memory cells to provide the local result data corresponding to one of a presence and absence of a defect, and for producing the result data corresponding to a defect if at least one of the local result data and previous result data corresponds to a defect.
16. The memory system of claim 15 , wherein the test circuit includes
a local comparison circuit for comparing the test data stored in at least two of the memory cells to each other to provide the local result data corresponding to a defect; and
a compression circuit for producing the result data corresponding to a defect if at least one of the local result data and the previous result data corresponds to a defect.
17. The memory system of claim 16 , wherein the result data, the local result data and the previous result data are each single-bit signals.
18. The memory system of claim 17 , wherein the local comparison circuit includes an exclusive OR circuit for comparing the test data stored in at least two of the memory cells to detect a defect.
19. The memory system of claim 17 , wherein the compression circuit includes an OR circuit for comparing the local result data with the previous result data to produce the result data.
20. The memory system of claim 18 , each of the serially connect memory devices includes a selector for selectively passing one of the result data and input data received at an input port to an output port.
21. The memory system of claim 13 , wherein the test pattern provider provides default pass data corresponding to an absence of a defect as the previous result data to a first memory device of the serially interconnected memory devices.
22. The memory system of claim 13 , wherein the test pattern receiver receives the result data from a last memory device of the serially interconnected memory devices.
23. An apparatus for testing a memory device having a serial input connection, and a serial output connection, the apparatus comprising:
a local comparison circuit for comparing data of at least two memory cells with each other, the local comparison circuit providing local result data corresponding to a fail status if one of the at least two memory cells is defective;
a compression circuit for compressing the local result data with global result data received from the serial input connection, for providing updated global result data to the serial output connection, the updated global result data corresponding to the fail status if at least one of the local result data and the global result data corresponds to the fail status.