Error detection method and a system including one or more memory devices
View Patent ↗A system including one or more memory devices, and an error detection and correction method are disclosed. A memory device of the system includes an input for receiving a packet. A first portion of the packet may include at least one command byte, and a second portion of the packet may include parity bits to facilitate command error detection. The memory device may include an error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte, and circuitry configured to provide the packet to the error manager.
1. A system comprising:
a plurality of serially interconnected semiconductor memory devices arranged in a point-to-point ring topology; and
a controller device to communicate with the semiconductor memory devices, the controller device comprising:
a command engine to generate a memory device-destined packet, a portion of the packet comprising at least one command byte;
an output to output the packet to a first device of the plurality of semiconductor memory devices;
an input to receive the packet from a last device of the plurality of semiconductor memory devices after having been communicated through each of the plurality of semiconductor memory devices arranged in the point-to-point ring topology; and
an error manager to determine, based on the received packet, whether an error occurred in transmission of the packet within the system, and
the command engine being configured to selectively reissue the packet if the error manager determines that the error occurred at a specific position in the ring topology.
2. The system as claimed in claim 1 , wherein each of the plurality of semiconductor memory devices include an error manager.
3. The system as claimed in claim 2 , wherein an at least one error manager of the plurality of semiconductor memory devices is configured to prevent execution of a command defined by the packet upon error detection.
4. The system as claimed in claim 1 , wherein the controller device is configured to receive an erroneously addressed device error byte, and the error manager is configured to process the erroneously addressed device error byte to determine whether a device before an intended target device was erroneously addressed.
5. The system as claimed in claim 1 , wherein the command engine is configured to cause re-issuance of a command if the device before the intended target device was erroneously addressed.
6. The system as claimed in claim 1 , wherein the command engine is capable of generating a broadcast command receivable by each of the plurality of semiconductor memory devices in order that information in a respective status register in each of the plurality of semiconductor memory devices may be provided in a sequential fashion to the controller device.
7. The system as claimed in claim 6 , wherein the error manager is configured to process each information of each status register to determine at which point in the ring topology the error occurred.
8. The system as claimed in claim 7 , wherein the command engine is further configured to reissue the packet if the error occurred before a target device.
9. The system as claimed in claim 1 , wherein the plurality of semiconductor memory devices are non-volatile memory devices.
10. The system as claimed in claim 9 , wherein the non-volatile memory devices are NAND flash memory devices.
11. The system as claimed in claim 1 , wherein the error manager is configured to calculate parity bits based on the portion of the packet as received and compares the calculated parity bits to another portion of the packet as received to determine whether the error occurred.
12. The system as claimed in claim 1 , wherein the error manager is configured to compare the received packet to the outputted packet to determine whether the error occurred.
13. The system as claimed in claim 1 , wherein the portion of the packet includes either a program command or an erase command.
14. The system as claimed in claim 1 , wherein another portion of the packet includes parity bits.
15. The system as claimed in claim 14 , wherein the parity bits facilitate command error correction.
16. The system as claimed in claim 14 , wherein the parity bits facilitate command error detection in accordance with a Hamming code error detection scheme.
17. The system as claimed in claim 15 , wherein each of the plurality of semiconductor memory devices includes a respective error manager to attempt correction of the packet if the error is detected.
18. The system as claimed in claim 17 , wherein, if the error is determined to have occurred, the error manager of the controller device is configured to determine whether the error in the received packet is correctable and reissue the packet if the error is not correctable.
19. The system as claimed in claim 18 , wherein the controller device is further configured to recognize that a single bit error in the received packet is correctable and a multiple bit error is not correctable.
20. A method carried out in a controller device that communicates with a plurality of serially interconnected semiconductor memory devices arranged in a point-to-point ring topology, the method comprising:
generating a memory device-destined packet, a portion of the packet comprising at least one command byte;
outputting the packet to a first device of the plurality of semiconductor memory devices;
receiving the packet from a last device of the plurality of semiconductor memory devices after having been communicated through each of the plurality of semiconductor memory devices arranged in the point-to-point ring topology; and
determining, based on the received packet, whether in transmission of the packet from the controller device, through the semiconductor memory devices and back to the controller device, an error occurred; and
selectively reissuing the packet if the error occurred at a specific position in the ring topology.
21. The method as claimed in claim 20 , further comprising generating a broadcast command for each of the plurality of semiconductor memory devices in order that information in a respective status register in each of the plurality of semiconductor memory devices may be provided in a sequential fashion to the controller.
22. The method as claimed in claim 21 , further comprising processing each information of each status register to determine at which point in the ring topology the error occurred.
23. The method as claimed in claim 22 , further comprising reissuing the packet if the error occurred before a target device.
24. The method as claimed in claim 20 , further comprising:
calculating parity bits based on the portion of the packet as received; and
comparing the calculated parity bits to another portion of the packet as received to determine whether the error occurred.
25. The method as claimed in claim 20 , further comprising comparing the received packet to the outputted packet to determine whether the error occurred.
26. The method as claimed in claim 20 , wherein the portion of the packet includes either a program command or an erase command.
27. The method as claimed in claim 20 , wherein another portion of the packet includes parity bits.
28. The method as claimed in claim 27 , wherein the parity bits facilitate command error correction.