Serial-connected memory system with output delay adjustment
View Patent ↗Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.
1. A method in a slave device of a plurality of serial-connected slave devices, the method comprising:
receiving a command from a master device specifying how the slave device is to adjust a delay to be applied to at least one input signal from the master device or a preceding serial-connected device to be output as at least one signal output by the slave device;
receiving the at least one input signal from the master device or a preceding serial-connected device, the at least one input signal comprising at least an input clock signal;
for each of the at least one input signal:
generating a delayed version of the input signal in accordance with the command;
outputting the delayed version of the input signal to the master device or a succeeding serial-connected device.
2. The method of claim 1 wherein the slave device is a memory device and the master device is a memory controller.
3. The method of claim 1 comprising:
outputting a data output signal;
wherein at least one of the input signals comprises a data input signal and wherein outputting the delayed version of the data input signal is performed as part of outputting the data output signal such that:
a) some of the time the data output signal is said delayed version of the data input signal;
b) some of the time the data output signal is a delayed version of a signal produced locally to the slave device, after applying the delay to the signal produced locally to the slave device in accordance with the command.
4. The method of claim 1 wherein receiving a command from a master device specifying an adjustment to a delay to be applied to at least one signal output by the slave device comprises receiving a command containing a command identifier that identifies the command as an output delay adjustment command, the command further containing data indicating how to adjust the delay.
5. The method of claim 4 wherein receiving a command further comprises receiving a device address indicating which device(s) acting as slave devices is to execute the command.
6. The method of claim 5 further comprising:
performing the step of, for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command if the command has a device address that matches a device address of the slave device;
performing the step of, for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command if the command has a device address that is a broadcast device address.
7. The method of claim 4 wherein:
for each input signal, generating a delayed version of the input signal comprises:
a) delaying the input signal by a selected one of a plurality of delays to produce the delayed version of the input signal.
8. The method of claim 7 wherein the data indicating how to adjust the delay comprises an indication of the selected one of the plurality of delays.
9. The method of claim 1 wherein the plurality of input signals comprise:
a clock signal;
a command strobe signal;
a data strobe signal;
a data signal containing commands and data.
10. A method in a memory system comprising a master device and a plurality of serial-connected device acting as slave devices comprising at least a first slave device and a last slave device, the method comprising:
in the master device:
a) outputting at least one output signal, the at least one output signal comprising a first clock signal to function as an input clock signal of the first slave device;
b) receiving a second clock signal that is an output clock signal of the last slave device;
c) determining an amount of phase offset between the first clock signal and the second clock signal;
d) generating an output delay adjustment command as a function of the phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command.
11. The method of claim 10 wherein each slave device is a memory device and the master device is a memory controller.
12. The method of claim 10 further comprising:
in the first slave device of the plurality of serial-connected device acting as slave devices:
a) receiving the at least one output signal from the master device as corresponding at least one input signal of the first slave device;
b) for each input signal, generating an output signal based on the input signal;
in each other slave device of the plurality of serial-connected device acting as slave devices:
a) receiving output signal(s) of a preceding slave device corresponding to at least one input signal of the slave device;
b) for each input signal, generating an output signal based on the input signal;
in at least one of the slave devices,
a) receiving the output delay adjustment command; and
b) generating the output signal(s) by generating a delayed version of the input signal(s) in accordance with the output delay adjustment command.
13. The method of claim 12 further comprising:
wherein the at least one output signal of the master device comprises a plurality of output signal(s).
14. The method of claim 10 wherein generating a delay adjustment command comprises generating a delay adjustment command for execution by a specified one of the plurality of serial-connected slave devices.
15. The method of claim 10 wherein generating a delay adjustment command comprises generating a delay adjustment command for execution by all of the plurality of serial-connected slave devices.
16. The method of claim 12 wherein generating a delayed version of the input signal(s) in accordance with the output delay adjustment command comprises generating a delayed version of the input signals(s) delayed by a selected one of a plurality of delays.
17. The method of claim 16 wherein generating a delay adjustment command comprises generating a command containing a command identifier that identifies the command as an output delay adjustment command, and containing data indicating how to adjust the delay.
18. The method of claim 17 wherein the data indicating how to adjust the delay comprises an indication of the selected one of the plurality of delays.
19. The method of claim 10 further comprising:
the master device outputting output delay adjustment commands that adjust delay by adding a delay one unit delay element in one slave device at a time until the phase offset is acceptable.
20. The method of claim 10 wherein the plurality of input signals comprise:
a clock signal;
a command strobe signal;
a data strobe signal;
a data signal containing commands and data.
21. A slave device for use in an arrangement comprising a plurality of serial-connected slave devices, the slave device comprising:
a command input for receiving a command from a master device specifying how to perform output delay adjustment;
a clock input for receiving an input clock signal from the master device or a preceding serial-connected device;
an output delay adjustment circuit for generating a delayed clock signal from the clock input in accordance with the command;
a clock output for outputting the delayed clock signal to the master device or a succeeding serial-connected device.
22. The slave device of claim 21 wherein the slave device is a memory device.
23. The slave device of claim 21 comprising:
a command processing circuit that processes the command, wherein the command contains a command identifier that identifies the command as an output delay adjustment command, and contains data indicating how to adjust the output delay.
24. The slave device of claim 23 further comprising:
a device address register;
wherein the command further comprises a device address indicating which slave device is to execute the command, the slave device configured to execute the command if the device identifier matches contents of the device address register.
25. The slave device of claim 21 wherein the output delay adjustment circuit comprises:
for each of a plurality of input signals, inclusive of the input clock signal, a delay circuit that delays the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal.
26. The slave device of claim 25 wherein each output delay circuit comprises M unit delay elements, M>=2, the duty cycle correction circuit further comprising:
an N-to-M decoder that decodes signals received on N input lines, N>=1, into a selection of how many of the unit delay elements are to be active in producing the delayed version of the input signal.
27. A memory system comprising:
a plurality of serial-connected slave devices according to claim 18 comprising at least a first slave device and a last slave device;
a master device connected to the first slave device and to the last slave device;
the master device configured to output a first clock signal that functions as an input clock signal of the first slave device;
a clock input for receiving a second clock signal that is an output clock signal of the last slave device;
a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal;
a command generator that generates an output delay adjustment command as a function of the amount of phase offset;
wherein, the first slave device of the plurality of serial-connected slave devices:
a) receives the first clock signal from the master device as the input clock signal of the first slave device;
b) generates an output clock signal from the input clock signal;
wherein each other slave device of the plurality of serial-connected slave devices:
a) receives the output clock signal of a preceding slave device as an input clock signal of the slave device;
b) generates an output clock signal from the input clock signal;
wherein at least one of the plurality of serial-connected slave devices:
a) receives the output delay adjustment command;
b) generates the output clock signal of the device by delaying the input clock signal of the device in accordance with the control command.
28. The system of claim 27 wherein the system is a memory system, each slave device is a memory device and the master device is a memory controller.
29. The memory system of claim 27 wherein the command generator is configured to generate the output delay adjustment command for execution by a specified one of the plurality of serial-connected slave devices.
30. The memory system of claim 27 wherein the command generator is configured to generate the output delay adjustment for execution by all of the plurality of serial-connected slave devices.
31. The memory system of 27 wherein generating an output delay adjustment command comprises generating a command containing a command identifier that identifies the command as an output delay adjustment command, and containing data indicating how to adjust the output delay.