Granted Patent B2

US 8,843,692 · App. 13/048,154 · Granted Sep 23, 2014

Abstract

Claims (75)

1. A memory device comprising:

a non-volatile memory array;

a data output port configured to output data read from the memory array;

a status maintainer configured to maintain status information identifying a status of the memory device;

a status transmitter configured to, responsive to a change in the status information, transmit a status signal using at least the data output port;

a first receiver configured to receive for receiving a first input signal;

a second receiver configured to receive for receiving a second input signal;

a first transmitter configured to transmit for transmitting a first output signal;

a second transmitter configured to transmit for transmitting a second output signal,

a command input being indicated by the first input signal asserted and the second input signal de-asserted,

a data input being indicated by the first input signal de-asserted and the second input signal asserted; and

an echo generator configured to cause the first output signal to be asserted after the first input signal is asserted, and cause the second output signal to be asserted after the second input signal is asserted,

the status transmitter, responsive to a change in the status information, transmitting the status signal using at least the data output port by:

transmitting the status information on the data output port;

causing the first output signal and the second output signal to be simultaneously asserted.

2. The memory device of claim 1 further comprising at least one other output port;

wherein the status signal that uses at least the data output port comprises a byte transmitted on the data output port, together with at least one indicator on the at least one other output port that indicates the byte being output on the data output port is a status byte.

3. The memory device of claim 1 wherein the status maintainer maintains status information that identifies whether the memory device is ready or busy, and wherein the status transmitter transmits the status information responsive to at least one of a change in status from busy to ready and a change in status from ready to busy.

4. The memory device of claim 1 wherein the memory device is one of a plurality of memory devices that are interconnected in series.

5. The memory device of claim 1 further comprising:

a status transmitter enabler that enables the status transmitter to transmit the status signal only when neither the first input signal nor the second input signal is being asserted.

6. The memory device of claim 1 wherein the device outputs a device ID as part of the status signal.

7. The memory device of claim 1 for use in an arrangement of serially interconnected like devices.

8. An apparatus comprising:

a plurality of memory devices in accordance with claim 1 in a serially interconnected arrangement including at least a first memory device and a last memory device;

a memory controller connected to the first and last of the plurality of memory device.

9. An apparatus comprising:

a memory controller;

a plurality of memory devices in accordance with claim 1 connected to the memory controller in a multi-drop configuration.

10. A memory device comprising:

a non-volatile memory array;

a data output port configured to output data read from the memory array;

a status maintainer configured to maintain status information identifying a status of the memory device;

a status transmitter configured to, responsive to a change in the status information, transmits a status signal;

a first receiver configured to receive a first input signal;

a second receiver configured to receive a second input signal;

a first transmitter configured to transmit a first output signal and a second transmitter configured for transmitting a second output signal;

wherein a command input is indicated by the first input signal being asserted and the second input signal being de-asserted;

wherein a data input is indicated by the first input signal being de-asserted and the second input signal being asserted;

the memory device further comprising an echo generator configured to cause the first output signal to be asserted after the first input signal is asserted, and causes the second output signal to be asserted after the second input signal is asserted;

wherein the status transmitter, responsive to a change in the status information, transmits the status signal by causing the first output signal and the second output signal to be simultaneously asserted.

11. A method comprising:

outputting data read from a memory array of a memory device through a data output port;

maintaining status information identifying a status of the memory device;

responsive to a change in the status information, transmitting a status signal using at least the data output port;

receiving a first input signal;

receiving a second input signal;

transmitting a first output signal and transmitting a second output signal;

a command input being indicated by the first input signal being asserted and the second input signal being de-asserted,

a data input being indicated by the first input signal being de-asserted and the second input signal being asserted;

causing the first output signal to be asserted after the first input signal is asserted; and

causing the second output signal to be asserted after the second input signal is asserted; and

responsive to a change in the status information, transmitting a status signal using at least the data output port, the transmitting comprising:

transmitting the status information on the data output port; and

causing the first output signal and the second output signal to be simultaneously asserted.

12. The method of claim 11 wherein transmitting the status signal comprises::

transmitting a byte on the data output port;

transmitting at least one indicator on at least one other output port configured to indicate the byte being output on the data output port is a status byte.

13. The memory device of claim 11 wherein the status information identifies whether the memory device is ready or busy, and transmitting the status information is responsive to at least one of a change in status from busy to ready and a change in status from ready to busy.

14. The method of claim 11 further comprising:

enabling the transmission of the status signal only when neither the first input signal nor the second input signal is being asserted.

15. The method of claim 11 further comprising:

outputting a device ID as part of the status signal.

16. The method of claim 11 for use in an arrangement of serially interconnected like devices.

17. The method of claim 11 for use in an arrangement of like memory devices connected to a memory controller in a multi-drop configuration.

18. A method comprising:

outputting data read from a memory array of a memory device through a data output port;

maintaining status information identifying a status of the memory device;

receiving a first input signal;

receiving a second input signal;

transmitting a first output signal and a transmitting a second output signal;

wherein a command input is indicated by the first input signal being asserted and the second input signal being de-asserted;

wherein a data input is indicated by the first input signal being de-asserted and the second input signal being asserted;

the method further comprising:

causing the first output signal to be asserted after the first input signal is asserted, and causing the second output signal to be asserted after the second input signal is asserted; responsive to a change in the status information, transmitting a status signal by causing the first output signal and the second output signal to be simultaneously asserted.

Assignments (9)