Data flow control in multiple independent port
A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
1. A memory device for use in a serial interconnection configuration comprising a plurality of memory devices connected in-series, each of the memory devices being addressable based on device identification (ID), the memory device comprising:
a receiver configured to receive an input port enable signal, a serial input signal and an output port enable signal, the receiver comprising:
a first input buffer configured to receive the input port enable signal and to provide an internal input enable signal;
a second input buffer configured to receive the serial input signal and to provide an internal serial input signal; and
a third input buffer configured to receive the output port enable signal and to provide an internal output enable signal; and
an output provider configured to output a serial output signal, an echo of the input port enable signal and an echo of the output port enable signal, the output provider comprises:
logic circuitry configured to
receive the internal serial input signal and the internal input enable signal, and
provide an input signal to a first flip-flop; and
a selector configured to
receive an output signal of the first flip-flop,
receive an internal serial output signal,
receive an ID match signal, and
select the output signal from the first flip-flop when the ID match signal is de-asserted or select the internal serial output signal when the ID match signal is asserted.
2. The memory device of claim 1 , wherein the selector is configured to provide the output signal from the first flip-flop or the internal serial output signal to a first output buffer.
3. The memory device of claim 2 , wherein the first output buffer is configured to receive a selected signal from the selector and output the serial output signal.
4. The memory device of claim 2 , wherein the first output buffer comprises a tri-state buffer configured to be enabled by a chip select signal.
5. The memory device of claim 1 , wherein the output provider further comprises:
a second flip-flop configured to receive the internal input enable signal and provide an input signal to a second output buffer; and
a third flip-flop configured to receive the internal output enable signal and provide an input signal to a third output buffer.
6. The memory device of claim 5 , wherein the first, second, and third flip-flops are configured to receive an internal clock signal.
7. The memory device of claim 5 , wherein the third output buffer is configured to output the echo of the output port enable signal.
8. The memory device of claim 1 , wherein the second output buffer is configured to output the echo of the input port enable signal.
9. The memory device of claim 1 , wherein the output provider further comprises:
a first output buffer configured to output the serial output signal;
a second output buffer configured to output the echo of the input port enable signal; and
a third input buffer configured to output the echo of the output port enable signal.
10. The memory device of claim 9 , wherein the first output buffer of the output provider comprises a tri-state buffer configured to be enabled by a chip select signal.
11. The memory device of claim 9 , wherein the output provider further comprises:
a second flip-flop configured to receive an internal input enable signal and provide an input signal to the second output buffer; and
a third flip-flop configured to receive an internal output enable signal and provide an input signal to the third output buffer.
12. The memory device of claim 11 , wherein the second input buffer is switchable by a chip select signal.
13. The memory device of claim 11 , wherein the third input buffer is switchable by a chip select signal.
14. The memory device of claim 11 , wherein the logic circuitry comprises an AND gate for logically combining the internal serial input signal; and the internal output enable signal.
15. The memory device of claim 1 , wherein the logic circuitry further comprises an AND gate for logically combining the internal serial input signal; and the internal output enable signal.