PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
1 - 29 . (canceled)
30 . An apparatus comprising a plurality of devices in a serial interconnection configuration, each of the plurality of devices having input and output connections, the serial interconnection configuration including at least first and second devices, the output connection of the first device being coupled to the input connection of the second device, the first device comprising:
a packet based processor comprising a clock producer responsive to an input clock to produce first and second clocks at different times, the packet based processor being configured:
to receive a first packet containing at least one packet start bit, an operation command for device identification production and a first device identifier number;
to interpret the operation command contained in the received first packet in synchronization with the first clock;
to produce a second device identifier number based on the first device identifier number in response to the at least one packet start bit contained in the received first packet and the interpreted operation command in synchronization with the second clock; and
to transfer a second packet containing the second device identifier number to the second device in synchronization with the input clock,
the clock producer comprising:
a clock generation controller configured to provide a command clock enable signal, an address clock enable signal, a data clock enable signal and an ID clock enable signal; and
a multiple clock generator configured to produce a command clock signal, an address clock signal, a data clock signal, and an ID clock signal, in response to the command clock enable signal, the address clock enable signal, the data clock enable signal, and the ID clock enable signal, respectively.