Apparatus and method for identifying device types of series-connected devices of mixed type
View Patent ↗A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.
1. A method for use in a system comprising a plurality of devices connected in-series in an interconnection configuration, each of the plurality of devices being associated with a device type, the method comprising:
providing a first signal including a first binary search number to a first device of the plurality of devices in the interconnection configuration, the first binary search number being represented by a pre-defined number of bits, the first signal being propagated through the plurality of devices,
incrementing the first binary search number included in the propagated first signal by each of the plurality of devices, an incremented first binary search number by each of the plurality of the devices replacing the first binary search number of the propagated first signal;
receiving the propagated first signal from a last device of the plurality in the interconnection configuration, the received propagated first signal including the first binary search number incremented by each of the plurality of devices;
recognizing the number of the plurality of devices in the interconnection configuration based on the first binary search number included in the received propagated first signal; and
in a case of the first binary search number included in the received propagated first signal being zero,
providing a second signal including a search device type and a second binary search number to the first device of the plurality of devices in the interconnection configuration, the second signal being propagated through the plurality of devices, at least one of the plurality of devices determining whether the search device type matches the device type associated with the device to provide a device type match determination result;
modifying the second binary search number included in the propagated second signal in response to the device type match determination result, a modified second binary search number replacing the second binary search number of the propagated second signal;
receiving the propagated second signal from the last device of the plurality of the interconnection configuration;
obtaining the number of the plurality of devices in the interconnection configuration based on the pre-defined number of bits representing the first binary search number of the first signal, in response to the search number included in the received propagated second signal.
2. The method of claim 1 , wherein the obtaining the number of the plurality of devices comprises:
verifying the modified second binary search number is different from the second binary search number included in the provided second signal.
3. The method of claim 1 , wherein each of the plurality of devices includes a memory for data store.
4. The method of claim 3 , wherein each of the plurality of devices has a device type corresponding to the type of the memory.
5. The method of claim 2 , wherein the providing a first signal comprises:
providing the first signal including the pre-defined bits representing the first binary search number of zero.
6. The method of claim 5 , wherein the providing a second signal comprises:
providing the second signal including the search device type and the second binary search number representing zero.
7. The method of claim 6 , wherein the obtaining the number of the plurality of devices comprises:
calculating the number N of the plurality of devices in the interconnection configuration by N=2 q , q being the pre-determined number of bits representing the first binary search number included in the first signal.
8. The method of claim 1 , wherein the plurality of devices include non-volatile memory devices and volatile memory devices.
9. The method of claim 1 , wherein the series-connected memory devices include random access memories.
10. The method of claim 9 , wherein the random access memories include dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM) and other semiconductor memories.
11. The method of claim 1 , wherein the series-connected memory devices include flash memories.
12. The method of claim 11 , wherein the flash memories include NAND-type, NOR-type, AND-type memories.