Mixed data rates in memory devices and systems
View Patent ↗Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first set of circuit elements are each clocked by a same or respective first internal signal having a frequency at least substantially equal to the frequency x. A second set of circuit elements are each clocked by a same or a respective second internal signal having a frequency at least substantially double that of the frequency x.
1. A system comprising:
at least one flash memory device and another device defining a ring topology; and
the flash memory device including:
i) input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x;
ii) a first set of circuit elements each clocked by a same or a respective first-type internal signal having a frequency at least substantially equal to the frequency x; and
iii) a second set of circuit elements each clocked by a same or a respective second-type internal signal having a frequency at least substantially double that of the frequency x.
2. The system of claim 1 wherein the flash memory device further includes a command strobe input and a command strobe output.
3. The system of claim 2 wherein the flash memory device further includes a driver and an electrical path, the electrical path extending from the command strobe input, through storage elements of the first set of circuit elements to the command strobe output, the first-type internal signal and the storage elements enabling the driver to provide a strobe signal at the command strobe output.
4. The system of claim 1 wherein the flash memory device further includes a clock synchronization unit, at least one clock output and clock driver circuitry, the clock synchronization unit for receiving the clock signal from the input circuitry and enabling the clock driver circuitry to provide delayed versions of the clock signal at the clock output.
5. The system of claim 1 wherein the flash memory device further includes a data strobe input, a data strobe output, at least one data input and at least one data output.
6. The system of claim 5 wherein the flash memory device further includes at least one data output driver and at least one internal data path, the internal data path for carrying write data internally clocked through storage elements of the second set of circuit elements, the data output driver for providing the write data on the data output.
7. The system of claim 6 wherein the another device is a memory controller, and the write data is transmitted to the flash memory device from the memory controller.
8. The system of claim 1 wherein the another device is a memory controller having output circuitry in electrical communication with the input circuitry of the flash memory device.
9. The system of claim 1 wherein the circuit elements of the first and second sets are D flip-flops.
10. The system of claim 1 wherein the at least one flash memory device is a plurality of flash memory devices.
11. The system of claim 1 wherein the input circuitry receives differential clock signals comprising the clock signal and another signal that is a complement of the clock signal.
12. A method carried out in a semiconductor memory device having at least one data input and at least one data output, the method comprising:
clocking read data, when a read operation occurs, out through the data output, and at a first rate at least double that of a second rate; and
bypassing received command data, when received and when determined that the command data is intended for a next downstream semiconductor memory device, the bypassing including clocking the command data out through the data output at the second rate.
13. The method of claim 12 further comprising:
receiving differential clock signals each of which has a frequency at least substantially equal to a frequency x.
14. The method of claim 13 further comprising:
producing, from the differential clock signals, an internal signal having a frequency at least substantially double that of the frequency x, the internal signal facilitating the clocking of the read data.
15. The method of claim 12 further comprising:
capturing write data, when a write operation occurs, at the first rate; and
in sequence with the capturing, transferring the write data to more permanent storage within the semiconductor memory device.
16. The method of claim 12 further comprising:
receiving write data at the data input;
determining whether the write data is intended for the next downstream semiconductor memory device; and
if the write data is intended for the next downstream semiconductor memory device, bypassing the received write data, the bypassing including clocking the write data out through the data output at the first rate.
17. The method of claim 12 wherein some bits of the command data provide device address information.
18. The method of claim 17 wherein the command data is intended for the next downstream semiconductor memory device if the device address information corresponds to a device address of the next downstream semiconductor memory device.
19. The method of claim 17 further comprising:
outputting from another output of the semiconductor memory device, a strobe that delineates a length of the command data provided at the data output.
20. A system comprising:
at least one semiconductor memory device and another device defining a ring topology; and
the semiconductor memory device including:
i) input circuitry for receiving a clock signal;
ii) a plurality of data input pins configured to receive both command data and other data at different times;
iii) first circuitry configured to employ the clock signal to clock in the other data, received on the data input pins, at a first rate at least double that of a second rate; and
iv) second circuitry configured to employ the clock signal to clock in the command data, received on the data input pins, at the second rate.
21. The system of claim 20 wherein the other data is write data.
22. The system of claim 20 wherein the semiconductor memory device further includes a clock synchronization unit, at least one clock output and clock driver circuitry, the clock synchronization unit for receiving the clock signal from the input circuitry and enabling the clock driver circuitry to provide delayed versions of the clock signal at the clock output.
23. The system of claim 22 wherein the clock synchronization unit comprises a phase locked loop or a delay locked loop.
24. The system of claim 20 wherein the another device is a memory controller and the at least one semiconductor memory device is a plurality of semiconductor memory devices.
25. The system of claim 20 wherein the input circuitry receives differential clock signals comprising the clock signal and another signal that is a complement of the clock signal.