Dynamic random access memory with fully independent partial array refresh function
View Patent ↗A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
1. A dynamic random access memory (DRAM) device comprising:
M memory, M being an integer greater than one, each having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshable by a refresh operation; and
a register for controlling, in a self-refresh mode, the refreshing of each of the M memory banks independently from each other;
wherein:
the register contains a respective bit for each memory bank which indicates whether or not, in a self-refresh mode, the memory bank is to be refreshed;
in self-refresh mode, the DRAM device performs a self-refresh operation only for the memory banks for which the respective bit in the register is set to indicate self-refresh.
2. The DRAM device of claim 1 , wherein the register comprises:
M latches, wherein each latch controls the refreshing of a respective one of the M memory banks.
3. A method for refreshing a dynamic random access memory device (DRAM) including M memory banks, M being an integer greater than one, each bank having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshable in a self-refresh mode, the method comprising:
controlling, in the self-refresh mode, the refreshing of each of the M memory banks independently from each other by:
storing in a register a respective bit for each memory bank which indicates whether or not, in a self-refresh mode, the memory bank is to be refreshed;
in self-refresh mode, performing a self-refresh operation only for the memory banks for which the respective bit in the register is set to indicate self-refresh.
4. The method of claim 3 , wherein the step of controlling comprises:
configuring M bank refresh data in response to input data, the M bank refresh data being independently set by the input data, each of the M bank refresh data controlling the refreshing at a respective one of the M memory banks.
5. A refresh controller for use in a dynamic random access memory (DRAM) device selectively operable in a self-refresh mode or a non self-refresh mode, the DRAM device including M memory banks, M being an integer greater that one, each banks having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshable in the self-refresh mode, the refresh controller comprising:
refresh circuitry for controlling, in the self-refresh mode, the refreshing of the memory banks independent from each other in accordance with M bank refresh data, the refresh circuitry comprising:
a register containing a respective bit for each memory bank which indicates whether or not, in a self-refresh mode, the memory bank is to be refreshed;
wherein in self-refresh mode, the refresh controller controls a self-refresh operation to occur only for the memory banks for which the respective bit in the register is set to indicate self-refresh.
6. The refresh controller of claim 5 , further comprising:
configuration circuitry for configuring the M bank refresh data in response to input data wherein each of the M bank refresh data corresponds to a respective one of the M memory banks.