Power supplies in flash memory devices and systems
View Patent ↗Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.
1. A flash memory device comprising:
a first section including flash memory for storing data; and
a second section configured to receive a supply voltage including:
i) a first pumping circuit being configured to increase the supply voltage produced under control of at least a first oscillation signal having a first output and a second pumping circuit connected to the output of the first pumping circuit being configured to increase the supply voltage produced therefrom under control of at least a second oscillation signal, different from the first oscillation signal having a second output at a different and higher voltage that the first output,
ii) first and second regulator circuits; and
iii) first and second oscillators for providing the first and second oscillation signals respectively, the first regulator circuit coupled to the first pumping circuit output, the first oscillator configured to receive an outputted voltage of the first regulator circuit, the second regulator circuit coupled to the second pumping circuit output, and the second oscillator configured to receive an outputted voltage of the second regulator circuit.
2. The flash memory device as claimed in claim 1 , wherein the first pumping circuit is configured to produce, at the first pumping circuit output, a first voltage required for carrying out a first type of memory operation, and the second pumping circuit being configured to produce, at the second pumping circuit output, a second voltage required for carrying out a second type of memory operation different than the first type of memory operation, and wherein the second pumping circuit pumps up from one transistor threshold voltage (Vtn) less than a voltage level of the first voltage.
3. The flash memory device as claimed in claim 2 , wherein the first and second types of memory operations are read and program operations respectively.
4. The flash memory device as claimed in claim 2 , wherein the second pumping circuit cooperatively employs the first pumping circuit to pump up from a voltage substantially greater than a voltage V.sub.DD.
5. The flash memory device as claimed in claim 4 , wherein the voltage V.sub.DD is 1.5V or less.
6. The flash memory device as claimed in claim 1 , wherein the first regulator circuit includes at least two voltage dividers and an operational amplifier.
7. The flash memory device as claimed in claim 1 , wherein the first regulator circuit includes trimming control circuitry.
8. The flash memory device as claimed in claim 1 , wherein the flash memory comprises an array of memory cells.
9. The flash memory device as claimed in claim 1 , wherein at least one of the first and second pumping circuits comprises a Dickson charge pump.
10. The flash memory device as claimed in claim 1 , further comprising at least one additional pumping circuit working in parallel with the first pumping circuit to provide for increased current, the at least one additional pumping circuit being at least substantially similar to the first pumping circuit.
11. The flash memory device as claimed in claim 1 , wherein the first and second oscillators comprise chains of inverters.
12. A method of producing voltages in a flash memory device having a first section including flash memory for storing data, and also having a second section that includes at least first and second pumping circuits, and first and second oscillators, the method comprising:
supplying, within the flash memory device, a first voltage at a first voltage level to the first pumping circuit;
producing, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level, the second voltage required for carrying out a first type of memory operation associated with the flash memory;
producing, at an output of the second pumping circuit a third voltage by increasing the output of the first pumping circuit a voltage greater than the first and second voltages, the third voltage at a third voltage level that is higher than the second voltage level, the third voltage required for carrying out a second type of memory operation associated with the flash memory, the second type of memory operation different than the first type of memory operation;
providing, from the first oscillator, an at least one oscillation signal to the first pumping circuits, the second voltage level increasing under control of the at least one oscillation signal;
and providing, from the second oscillator, an at least another oscillation signal to the second pumping circuit, the at least another oscillation signal different than the at least one oscillation signal, and the third voltage level increasing under control of the at least another oscillation signal.
13. The method as claimed in claim 12 , wherein the first and second types of memory operations are read and program operations respectively.
14. The method as claimed in claim 12 , wherein the first voltage is a voltage V.sub.DD.
15. The method as claimed in claim 14 , wherein the voltage V.sub.DD is 1.5V or less.
16. The method as claimed in claim 12 , wherein the second type of memory operation is an erase operation.