Semiconductor memory device and driving method thereof
View Patent ↗A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.
1. A semiconductor memory device, comprising:
a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock;
an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and
a calibration controller for controlling the predetermined delay time of the variable delay according to output AC parameters,
wherein the calibration controller comprises:
a feedback input buffer for feeding back the data and the data strobe signal, which are being transferred to a chipset, in response to a calibration test mode signal generated when a calibration command is received; and
a timing measurer for receiving the data and the data strobe signal from the feedback input buffer and control the predetermined delay time by measuring the output AC parameters.
2. The semiconductor memory device of claim 1 , wherein the calibration controller controls the predetermined delay time according to measured values of the output AC parameters, the measured values being received from the chipset.
3. The semiconductor memory device of claim 1 , wherein the calibration controller comprises:
a real-time monitor for monitoring the data and the data strobe signal being transferred to the chipset; and
a timing measurer for receiving the data and the data strobe signal from the real-time monitor and controlling the predetermined delay time by measuring the output AC parameters.
4. The semiconductor memory device of claim 1 , wherein the output driver comprises:
a pre-driver for pre-driving an output data signal; and
a main driver for driving a data output terminal in response to an output signal of the pre-driver.
5. The semiconductor memory device of claim 1 , wherein the output AC parameters include at least one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock.
6. A method for driving a semiconductor memory device, comprising:
measuring output AC parameters;
setting a delay value with respect to a delay locked loop (DLL) clock in response to the measured values of the output AC parameters;
delaying the DLL clock by the delay value to output a delayed DLL clock; and
outputting data strobe signal and data having calibrated output AC parameters in response to the delayed DLL clock,
wherein the measuring of the output AC parameters comprises:
generating a calibration test mode signal in response to a calibration command:
feeding back the data and the data strobe signal of being transmitted to a chipset in response to the calibration test mode signal; and
measuring the output AC parameters by using the fed-back data strobe signal and the fed-back data.
7. The method of claim 6 , wherein the measuring of the output AC parameters includes:
transmitting the data and the data strobe signal to the chipset in response to the calibration command; and
receiving the output AC parameters measured at the chipset by using the data strobe signal and the data.
8. The method of claim 6 , wherein the measuring of the output AC parameters comprises:
monitoring in real time the data and the data strobe signal of being transmitted to the chipset; and
measuring the output AC parameters by using the data and the data strobe signal.
9. The method of claim 6 , further comprising completing a calibration operation when the output AC parameters remeasured at the chipset based on the data and the data strobe signal having the calibrated output AC parameters comply with a specification.
10. The method of claim 6 , further comprising returning to the receiving of the output AC parameters when the output AC parameters remeasured at the chipset based on the data and the data strobe signal having the calibrated output AC parameters do not comply with a specification.
11. The method of claim 6 , wherein the output AC parameters include at least one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock.