Patent Assignment
Reel/Frame 033707/0001
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Recorded: 2014-09-09
Pages: 110
Assignor
CONVERSANT IP N.B. 868 INC.
Executed: 2014-06-11
Assignees
CPPIB CREDIT INVESTMENTS INC., AS LENDER
QUEEN STREET EAST, SUITE 2500, TORONTO, M5C 2W5, CANADA
ROYAL BANK OF CANADA, AS LENDER
20 KING STREET WEST, 4TH FLOOR, TORONTO, M5H 1C4, CANADA
Covered Properties
(185)
Method for Forming a Two-Layered Polysilicon Gater Electrode in a Semiconductor Device Using Grain Boundaries
Patent:
5,441,904 →
Application:
08/341,892 →
Method for Forming an Oxynitride Film in a Semiconductor Device
Patent:
5,541,141 →
Application:
08/394,607 →
Wiring Structure for Semiconductor Device and Fabrication Method Therefor
Patent:
5,656,860 →
Application:
08/494,645 →
Method for Fabricating Semiconductor Memory Element
Patent:
5,654,223 →
Application:
08/495,270 →
Semiconductor Device Fabrication Method
Patent:
5,882,968 →
Application:
08/576,752 →
Interconnection Structure for Attaching a Semiconductor Device to a Substrate
Patent:
5,703,406 →
Application:
08/587,744 →
Renumbered Array Architecture for Multi-Array Memories
Patent:
5,859,961 →
Application:
08/656,164 →
Sense Amplifier with Low Power in a Semiconductor Device
Patent:
5,781,041 →
Application:
08/669,746 →
Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
5,702,970 →
Application:
08/670,592 →
Method for Manufacturing Mosfet
Patent:
5,759,900 →
Application:
08/708,742 →
Semiconductor Memory Device
Patent:
5,757,692 →
Application:
08/727,852 →
Method for Fabricating a Semiconductor Device Having a Tapered Contact Hole
Patent:
6,107,138 →
Application:
08/744,805 →
Method for Removing Defects by Ion Implantation Using Medium Temperature Oxide Layer
Patent:
5,846,887 →
Application:
08/757,161 →
Method for Fabricating a Capacitor of a Semiconductor Device and the Structure of the Same
Patent:
5,714,402 →
Application:
08/757,246 →
Sub Word Line Driving Circuit and a Semiconductor Memory Device Using the Same
Patent:
5,781,498 →
Application:
08/764,083 →
Fabrication Method of Semiconductor Memory Device Containing Cmos Transistors
Patent:
5,696,012 →
Application:
08/772,851 →
Method for Fabricating a Semiconductor Device
Patent:
6,261,882 →
Application:
08/773,174 →
Thin Film Transistor for Antistatic Circuit and Method for Fabricating the Same
Patent:
5,807,728 →
Application:
08/774,824 →
Synchronous Memory Device Having Dual Input Registers of Pipeline Structure in Data Path
Patent:
5,796,675 →
Application:
08/796,219 →
Method for Forming an Oxynitride Film in a Semiconductor Device
Patent:
37,960 →
Application:
08/824,879 →
Word Line Driver for Semiconductor Memories
Patent:
5,875,149 →
Application:
08/828,817 →
Method for Forming Contact Hole of Semiconductor Device
Patent:
5,869,404 →
Application:
08/847,811 →
Method and Circuit for Generating Internal Pulse Signals in Synchronous Memory
Patent:
5,781,500 →
Application:
08/850,247 →
Interconnection Structure for Attaching a Semiconductor to Substrate
Patent:
5,883,438 →
Application:
08/854,069 →
Wiring Structure for Semiconductor Device and Fabrication Method Therefor
Patent:
6,057,232 →
Application:
08/862,926 →
A Semiconductor Memeory Device Having Plural Memory Cell Arrays Divided into Plural Bank Sections
Patent:
6,209,056 →
Application:
08/885,035 →
Sub Word Line Driving Circuit and a Semiconductor Memory Device Using the Same
Patent:
5,835,439 →
Application:
08/887,280 →
A Trench Isolation Structure of a Semiconductor Device and a Method for Thereof
Patent:
5,994,200 →
Application:
08/898,574 →
Method for Isolating Semiconductor Devices
Patent:
6,060,399 →
Application:
08/923,108 →
A Method for Developing Shallow Trench Isolation in a Semiconductor Memory Device
Patent:
5,904,538 →
Application:
08/923,141 →
Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
5,953,576 →
Application:
08/925,060 →
Clock Signal Phase Comparator
Patent:
6,087,857 →
Application:
08/943,184 →
Low Voltage Transistor Structure Having a Grooved Gate
Patent:
6,091,106 →
Application:
08/957,781 →
Semiconductor Apparatus Having a Leadframe with Coated Leads
Patent:
5,923,080 →
Application:
08/960,081 →
Memory Device Having Divided Global Bit Lines
Patent:
5,864,497 →
Application:
08/961,544 →
Semiconductor Chip Package and Method for Fabricating the Same
Patent:
6,140,700 →
Application:
08/966,703 →
A Method for Fabricating a Semiconductor Device
Patent:
5,985,734 →
Application:
08/979,235 →
Cell Array and Sense Amplifier Structure Exhibiting Improved Noise Characteristic and Reduced Size
Patent:
6,002,625 →
Application:
08/991,618 →
Method for Fabricating Field Effect Transistor
Patent:
6,017,801 →
Application:
09/006,479 →
Planarization Method for a Semiconductor Device
Patent:
6,117,787 →
Application:
09/013,095 →
Method of Fabrication a Source/Drain with Ldd and Halo
Patent:
5,937,293 →
Application:
09/057,537 →
Ball Grid Array Package
Patent:
6,060,778 →
Application:
09/060,981 →
Method of Fabricating Gate Electrodes of Twin-Well Cmos Device
Patent:
6,103,603 →
Application:
09/065,487 →
Synchronous Dynamic Random Access Memory in a Semiconductor Memory Device
Patent:
6,064,619 →
Application:
09/106,308 →
Thin Film Transistor for Antistatic Circuit and Method for Fabricating the Same
Patent:
6,207,997 →
Application:
09/127,443 →
Method for Manufacturing a Capacitor of a Semiconductor Device
Patent:
6,066,540 →
Application:
09/143,096 →
Semiconductor Device Having Capacitor
Patent:
6,034,392 →
Application:
09/151,601 →
Method for Fabricating a Surface Mounting Type Semiconductor Chip Package
Patent:
6,162,664 →
Application:
09/168,886 →
Word Line Driver for Semiconductor Memories
Patent:
6,011,746 →
Application:
09/182,943 →
Method of Preventing Bowing in a via Formation Process
Patent:
6,124,208 →
Application:
09/186,354 →
Adjusable Substrate Voltage Applying Circuit of a Semiconductor Device
Patent:
6,150,870 →
Application:
09/195,202 →
Delay Locked Loop Device of the Semiconductor Circuit
Patent:
6,154,073 →
Application:
09/196,121 →
Semiconductor Device and Method of Fabricating the Same
Semiconductor Device Having Improved on-Off Current Characteristics
Patent:
6,291,865 →
Application:
09/217,574 →
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Patent:
6,291,259 →
Application:
09/239,152 →
Circuit for Standby Current Reduction
Patent:
6,288,586 →
Application:
09/243,469 →
Plural Memory Banks Memory Device That Can Simultaneously Read from or Write to All of the Memory Banks During Testing
Patent:
6,198,667 →
Application:
09/290,399 →
Phase Splitter
Patent:
6,292,042 →
Application:
09/295,403 →
Sense Amplifier Driving Device
Patent:
6,144,230 →
Application:
09/317,113 →
Semiconductor Device for Improving Short Channel Effect
Patent:
6,078,081 →
Application:
09/326,694 →
Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
6,080,594 →
Application:
09/336,698 →
Method of Forming Capacitor of Semiconductor Device
Patent:
6,207,496 →
Application:
09/362,210 →
Method for Fabricating Contact Pad for Semiconductor Device
Patent:
6,297,091 →
Application:
09/397,136 →
Etch Barrier Structure of a Semiconductor Device and Method for Fabricating the Same
Patent:
6,262,467 →
Application:
09/410,613 →
Semiconductor Chip Package and Method of Fabricating Same
Patent:
6,458,627 →
Application:
09/415,267 →
Capacitor for Semiconductor Memory Device and Fabrication Method Thereof
Patent:
6,342,425 →
Application:
09/417,775 →
Analog Mixed Digital Dll
Patent:
6,392,456 →
Application:
09/427,272 →
Method for Fabricating Semiconductor Device
Impurity Ion Segregation Precluding Layer, Fabrication Method Thereof, Isolation Structure for Semiconductor Device Using the Impurity Ion Segregation Precluding Layer and Fabricating Method Thereof
Patent:
6,337,256 →
Application:
09/441,206 →
Method for Forming Gate Oxide Film in Semiconductor Device
Patent:
6,355,579 →
Application:
09/442,736 →
A Semiconductor Memory Array Layout
Patent:
6,329,678 →
Application:
09/451,852 →
Semiconductor Device Having Capacitor and Method of Fabricating the Same
Patent:
6,242,316 →
Application:
09/457,340 →
Apparatus and Method for Performing Data Read Operation in Ddr Sdram
Patent:
6,201,760 →
Application:
09/461,718 →
Multi-Chip Package
Patent:
6,121,682 →
Application:
09/469,131 →
Delay Locked Loop Using Bidirectional Delay
Patent:
6,239,641 →
Application:
09/476,380 →
Semiconductor chip package and method for fabricating the same
Patent:
6,214,648 →
Application:
09/604,762 →
Method for forming multi-layer interconnection of a semiconductor device
Patent:
6,313,029 →
Application:
09/606,874 →
Method for fabricating a semiconductor memory device
Patent:
6,350,650 →
Application:
09/710,958 →
Method of Forming a Gate Electrode in a Semiconductor Device
Patent:
6,514,826 →
Application:
09/721,636 →
Semiconductor Memory Device Incorporating Therein Ruthenium Electrode and Method for the Manufacture Thereof
Delay Locked Loop for Use in Semiconductor Memory Device
Delay Locked Loop with Delay Control Unit for Noise Elimination
Semiconductor Memory Device Having Capacitor Structure Formed in Proximity to Corresponding Transistor
Column Transistor for Semiconductor Devices
Semiconductor Memory Device Having a Plurality of Banks Sharing a Column Control Unit
Method for Fabricating Semiconductor Device Having a Capacitor
Method for forming a gate electrode on a semiconductor substrate
Patent:
6,306,743 →
Application:
09/798,942 →
Semiconductor device and method for fabricating the same
Method of Forming a Metal Wiring in a Semiconductor Device with Copper Seed
Method for Making High K Dielectric Gate for Semiconductor Device
Mosfet Device Fabrication Method Capable of Allowing Application of Self-Aligned Contact Process While Maintaining Metal Gate to Have Uniform Thickness
Delay Locked Loop Incorporating a Ring Type Delay and Counting Elements
Self Refresh Circuit for Semiconductor Memory Device
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Method of Forming Dual-Metal Gates in Semiconductor Device
Circuit and Method for Controlling Buffers in Semiconductor Memory Device
Capacitor for Semiconductor Memory Device
Patent:
6,507,062 →
Application:
10/013,402 →
Low Power Semiconductor Memory Device Having a Normal Mode and a Partial Array Self Refresh Mode
Circuit for Generating Internal Address in Semiconductor Memory Device
Method of Manufacturing Semiconductor Devices with Titanium Aluminum Nitride Work Function
Duty Correction Circuit and a Method of Correcting a Duty
Patent:
6,525,581 →
Application:
10/033,989 →
Method of Forming a Contact Plug for a Semiconductor Device
Patent:
6,472,303 →
Application:
10/034,242 →
Method of Manufacturing a Contact Plug for a Semiconductor Device
Duty Cycle Correction Circuit
Method of Forming a Metal Gate in a Semiconductor Device Using Atomic Layer Deposition Process
Apparatus and Method for Operation of Multi-Bank Semiconductor Memory Device with an Up/Down Counter
Method for Forming Wire in Semiconductor Device
Delay Circuit of Clock Synchronization Device Using Delay Cells Having Wide Delay Range
Semiconductor Device Having a Metal Insulator Metal Capacitor
Method of Forming Contact Holes in Semiconductor Devices and Method of Forming Capacitors Using the Same
Register Controlled Dll Reducing Current Consumption
Semiconductor Chip Package and Method of Fabricating Same
Method for Fabricating Capacitors in Semiconductor Devices
Cmos of Semiconductor Device and Method for Manufacturing the Same
Damascene Capacitor Formed in Metal Interconnection Layer
Gate Structure with High K Dielectric
Method of Manufacturing Semiconductor Devices
Delay Model Circuit for Use in Delay Locked Loop
Method for Forming Contact Plug in Semiconductor Device
Refresh Control Circuit and Method for Semiconductor Memory Device
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
Method for Fabricating Metal-Oxide Semiconductor Transistor
Duty Cycle Correction Circuit and Delay Locked Loop Having the Same
High Voltage Supply Circuit and a Method of Supplying High Voltage
Cmos of Semiconductor Device and Method for Manufacturing the Same
Method of Fabricating Dielectric Layer
Semiconductor Memory Device with Modified Global Input/Output Scheme
Semiconductor Device and Method for Fabricating the Same
Data Output Control Circuit
Semiconductor Memory Device Having Row Path Control Circuit and Operating Method Thereof
Method for Forming Conductive Line of Semiconductor Device
Method for Forming Polysilicon Plug of Semiconductor Device
Memory Apparatus Having Multi-Port Architecture for Supporting Multi Processor
On Die Termination Mode Transfer Circuit in Semiconductor Memory Device and Its Method
Write Circuit of Double Data Rate Synchronous Dram
Method for Detecting Column Fail by Controlling Sense Amplifier of Memory Device
Apparatus and Method of Compensating for Phase Delay in Semiconductor Device
Method for Fabricating Semiconductor Device
Semiconductor Memory Device
Voltage Regulating Circuit and Method of Regulating Voltage
Semiconductor Memory Device with Efficient Multiplexing of I/O Pad in Multi-Chip Package
Semiconductor Memory Device for Low Power System
Delay Locked Loop and Locking Method Thereof
Patent:
6,943,602 →
Application:
11/026,970 →
Main Amplifier and Semiconductor Device
Method for Manufacturing Semiconductor Device
Semiconductor Memory Device for Simultaneously Testing Blocks of Cells
Method for Forming Storage Node of Capacitor in Semiconductor Device
Method of Inhibiting Degradation of Gate Oxide Film
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
Method for Manufacturing Semiconductor Device
Semiconductor Memory Device
Semiconductor Device and Method for Fabricating a Semiconductor Device
Semiconductor Memory Device
Method for Fabricating a Semiconductor Device
Method of Manufacturing Semiconductor Device
Transistor of Semiconductor Memory Device
Five Channel Fin Transistor and Method for Fabricating the Same
On-Die Termination Apparatus
Semiconductor Memory Device Sharing a Data Line Sense Amplifier and a Write Driver in Order to Reduce a Chip Size
Data Input Circuit of Semiconductor Memory Device and Data Input Method Thereof
Pmos Transistor of Semiconductor Device, Semiconductor Device Comprising the Same, and Method for Manufacturing the Same
Method for Fabricating Semiconductor Device Having Capacitor
Semiconductor Memory Device and Driving Method Thereof
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
On-Die Termination Circuit and Driving Method Thereof
Method for Forming Storage Node of Capacitor in Semiconductor Device
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
Semiconductor Device with Recess and Fin Structure
On-Die Termination Circuit and Driving Method Thereof
Data Bus Line Control Circuit
Patent:
44,051 →
Application:
13/335,207 →
Semiconductor Memory Device for Controlling Write Recovery Time
Patent:
44,218 →
Application:
13/335,234 →
Method of Manufacturing Semiconductor Device with Recess and Fin Structure
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Patent:
44,230 →
Application:
13/367,023 →
Clock Control Device for Toggling an Internal Clock of a Synchronous Dram for Reduced Power Consumption
Patent:
44,590 →
Application:
13/369,988 →
Semiconductor Memory Device and Driving Method Thereof
Patent:
44,632 →
Application:
13/538,130 →
Method of Forming a Contact Plug for a Semiconductor Device
Patent:
45,232 →
Application:
13/568,920 →
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Patent:
44,532 →
Application:
13/586,272 →
On-Die Termination Circuit and the Driving Method Thereof
Patent:
45,246 →
Application:
13/706,541 →
Semiconductor Memory Device
Patent:
45,036 →
Application:
13/779,097 →
Semiconductor Memory Device for Controlling Write Recovery Time
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Method of Preventing Bowing in a via Formation Process
Application:
14/025,073 →
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Semiconductor Memory Device and Driving Method Thereof
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Application:
14/257,513 →
Publication:
US 2014/0226421
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: 658868 N.B. INC.
To: CONVERSANT IP N.B. 868 INC.
Reel/Frame 032439/0547 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Assignment of Assignor's Interest
Jul 22, 2015
From: CONVERSANT IP N.B. 868 INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 036159/0386 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →