Semiconductor memory device for controlling write recovery time
View Patent ↗A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
1. A method of controlling timing of a precharge operation according to a CAS latency mode, the method comprising:
detecting the CAS latency mode;
outputting a delay signal corresponding to the CAS latency mode;
outputting a delayed auto-precharge signal after delaying an auto-precharge signal by passing the auto-precharge signal through one or more unit delays; and
performing an auto-precharge operation synchronized to a clock signal in response to the delayed auto-precharge signal, wherein the number of the unit delays where the auto-precharge signal passes through is determined by the delay signal.
2. The method of claim 1 , wherein:
outputting a delay signal comprises outputting a plurality of delay signals.
3. The method of claim 2 , wherein:
outputting a plurality of delay signals comprises outputting a plurality of control signals to a precharge timing decoder.
4. The method of claim 3 , wherein:
outputting a plurality of delay signals further comprises outputting the plurality of delay signals from the precharge timing decoder to an auto-precharge timing unit.
5. The method of claim 4 , wherein:
outputting the plurality of delay signals comprises outputting the plurality of delay signals from the precharge timing decoder in response to the plurality of control signals.
6. The method of claim 2 , wherein the range of CAS latencies covers the range from 2 to 5.
7. The method of claim 2 , wherein the plurality of delay signals correspond to CAS latency 2, 3, 4, and 5.
8. The method of claim 1 , further comprising:
selectively blowing a fuse during wafer-level test; and
detecting whether the fuse was blown, wherein the auto-precharge signal passes through a number of unit delays determined by the delay signal and whether the fuse was blown.
9. The method of controlling timing according to claim 8 , wherein the fuse is a plurality of fuses.
10. The method of controlling timing according to claim 1 , wherein the auto-precharge signal passes through a number of unit delays determined by the delay signal and the state of a fuse.
11. The method of controlling timing according to claim 10 , wherein the fuse is a plurality of fuses.
12. The method of controlling timing according to claim 1 , wherein the one or more unit delays are synchronous delays.
13. The method of controlling timing according to claim 1 , wherein the one or more unit delays are asynchronous delays.
14. The method of controlling timing according to claim 1 , wherein the one or more unit delays are mixed synchronous and asynchronous delays.
15. The method of controlling timing according to claim 1 , wherein the one or more unit delays are a plurality of serially connected unit delays.
16. The method of controlling timing according to claim 15 , wherein a first unit delay of the plurality of serially connected unit delays receives the auto-precharge signal and provides a first output signal, and a second unit delay of the plurality of serially connected unit delays receives the first output signal and provides a second output signal.
17. The method of controlling timing according to claim 16 , wherein the delay signal comprises a first and second decoded signal and the first output signal is transferred as the delayed auto-precharge signal when the first decoded signal is activated and the second output signal is transferred as the delayed auto-precharge signal when the second decoded signal is activated.
18. The method of controlling timing according to claim 17 , wherein the auto-precharge signal is transferred as the delayed auto-precharge signal when the first and second decoded signals are inactivated.