Patent Assignment
Reel/Frame 054371/0884
Release of Security Interest
Recorded: 2020-11-10
Pages: 75
Assignor
CPPIB CREDIT INVESTMENTS INC.
Executed: 2020-10-28
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, K2K 3G4, CANADA
Covered Properties
(68)
Semiconductor Device Having Capacitor
Patent:
6,034,392 →
Application:
09/151,601 →
Method of Preventing Bowing in a via Formation Process
Patent:
6,124,208 →
Application:
09/186,354 →
Adjusable Substrate Voltage Applying Circuit of a Semiconductor Device
Patent:
6,150,870 →
Application:
09/195,202 →
Delay Locked Loop Device of the Semiconductor Circuit
Patent:
6,154,073 →
Application:
09/196,121 →
Semiconductor Device and Method of Fabricating the Same
Semiconductor Device Having Improved on-Off Current Characteristics
Patent:
6,291,865 →
Application:
09/217,574 →
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Patent:
6,291,259 →
Application:
09/239,152 →
Circuit for Standby Current Reduction
Patent:
6,288,586 →
Application:
09/243,469 →
Phase Splitter
Patent:
6,292,042 →
Application:
09/295,403 →
Method of Forming Capacitor of Semiconductor Device
Patent:
6,207,496 →
Application:
09/362,210 →
Semiconductor Chip Package and Method of Fabricating Same
Patent:
6,458,627 →
Application:
09/415,267 →
Capacitor for Semiconductor Memory Device and Fabrication Method Thereof
Patent:
6,342,425 →
Application:
09/417,775 →
Method for Fabricating Semiconductor Device
Impurity Ion Segregation Precluding Layer, Fabrication Method Thereof, Isolation Structure for Semiconductor Device Using the Impurity Ion Segregation Precluding Layer and Fabricating Method Thereof
Patent:
6,337,256 →
Application:
09/441,206 →
Method for Forming Gate Oxide Film in Semiconductor Device
Patent:
6,355,579 →
Application:
09/442,736 →
Semiconductor Device Having Capacitor and Method of Fabricating the Same
Patent:
6,242,316 →
Application:
09/457,340 →
Multi-Chip Package
Patent:
6,121,682 →
Application:
09/469,131 →
Delay Locked Loop Using Bidirectional Delay
Patent:
6,239,641 →
Application:
09/476,380 →
Method for forming multi-layer interconnection of a semiconductor device
Patent:
6,313,029 →
Application:
09/606,874 →
Method of Forming a Gate Electrode in a Semiconductor Device
Patent:
6,514,826 →
Application:
09/721,636 →
Semiconductor Memory Device Incorporating Therein Ruthenium Electrode and Method for the Manufacture Thereof
Semiconductor Memory Device Having Capacitor Structure Formed in Proximity to Corresponding Transistor
Method for Fabricating Semiconductor Device Having a Capacitor
Method for forming a gate electrode on a semiconductor substrate
Patent:
6,306,743 →
Application:
09/798,942 →
Method of Forming a Metal Wiring in a Semiconductor Device with Copper Seed
Mosfet Device Fabrication Method Capable of Allowing Application of Self-Aligned Contact Process While Maintaining Metal Gate to Have Uniform Thickness
Delay Locked Loop Incorporating a Ring Type Delay and Counting Elements
Self Refresh Circuit for Semiconductor Memory Device
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Circuit and Method for Controlling Buffers in Semiconductor Memory Device
Capacitor for Semiconductor Memory Device
Patent:
6,507,062 →
Application:
10/013,402 →
Low Power Semiconductor Memory Device Having a Normal Mode and a Partial Array Self Refresh Mode
Method of Manufacturing Semiconductor Devices with Titanium Aluminum Nitride Work Function
Duty Correction Circuit and a Method of Correcting a Duty
Patent:
6,525,581 →
Application:
10/033,989 →
Method of Manufacturing a Contact Plug for a Semiconductor Device
Duty Cycle Correction Circuit
Apparatus and Method for Operation of Multi-Bank Semiconductor Memory Device with an Up/Down Counter
Method for Forming Wire in Semiconductor Device
Semiconductor Device Having a Metal Insulator Metal Capacitor
Register Controlled Dll Reducing Current Consumption
Cmos of Semiconductor Device and Method for Manufacturing the Same
Method for Fabricating Metal-Oxide Semiconductor Transistor
High Voltage Supply Circuit and a Method of Supplying High Voltage
Method of Fabricating Dielectric Layer
Data Output Control Circuit
Method for Forming Conductive Line of Semiconductor Device
Memory Apparatus Having Multi-Port Architecture for Supporting Multi Processor
Write Circuit of Double Data Rate Synchronous Dram
Apparatus and Method of Compensating for Phase Delay in Semiconductor Device
Method for Fabricating Semiconductor Device
Voltage Regulating Circuit and Method of Regulating Voltage
Semiconductor Memory Device for Low Power System
Semiconductor Memory Device for Simultaneously Testing Blocks of Cells
Method of Inhibiting Degradation of Gate Oxide Film
Method for Manufacturing Semiconductor Device
Semiconductor Device and Method for Fabricating a Semiconductor Device
Method of Manufacturing Semiconductor Device
Pmos Transistor of Semiconductor Device, Semiconductor Device Comprising the Same, and Method for Manufacturing the Same
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
Semiconductor Memory Device for Controlling Write Recovery Time
Patent:
44,218 →
Application:
13/335,234 →
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Patent:
44,230 →
Application:
13/367,023 →
On-Die Termination Circuit and the Driving Method Thereof
Patent:
45,246 →
Application:
13/706,541 →
Semiconductor Memory Device
Patent:
45,036 →
Application:
13/779,097 →
Semiconductor Memory Device for Controlling Write Recovery Time
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Method of Preventing Bowing in a via Formation Process
Application:
14/025,073 →
Semiconductor Memory Device and Driving Method Thereof
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: 658868 N.B. INC.
To: CONVERSANT IP N.B. 868 INC.
Reel/Frame 032439/0547 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT IP N.B. 868 INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033707/0001 →
Assignment of Assignor's Interest
Jul 22, 2015
From: CONVERSANT IP N.B. 868 INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 036159/0386 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →