Semiconductor memory device for low power system
View Patent ↗An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar. A precharge block precharges the bit line and the bit line bar at a ground. A sense amplifying block senses and amplifies the data by using a low voltage having a lower voltage level than the ground and a high voltage having a higher voltage level than a supply voltage.
1. An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar, comprising:
a precharge means for precharging the bit line and the bit line bar as a ground; and
a sense amplifying means for sensing and amplifying the data by using a low voltage having a lower voltage level than the ground and a high voltage having a higher voltage level than a supply voltage.
2. The apparatus as recited in claim 1 , wherein the supply voltage and the ground are inputted outside of the semiconductor memory device.
3. The apparatus as recited in claim 2 , further comprising an internal voltage generator for receiving the supply voltage and the ground to thereby generate the low voltage and the high voltage.
4. The apparatus as recited in claim 3 , further comprising:
a first voltage supplying block for supplying one of the low voltage and the ground to the sense amplifying means in response to a first power control signal and a second power control signal; and
a second voltage supplying block for supplying one of the high voltage and the ground to the sense amplifying means in response to a third power control signal and the second power control signal.
5. The apparatus as recited in claim 4 , wherein the first voltage supplying block includes:
a first MOS transistor for outputting the high voltage to the sense amplifying means in response to the first power control signal; and
a second MOS transistor for outputting the ground to the sense amplifying means in response to the second power control signal.
6. The apparatus as recited in claim 5 , wherein the second voltage supplying block includes:
a third MOS transistor for outputting the low voltage to the sense amplifying means in response to the third power control signal; and
a fourth MOS transistor for outputting the ground to the sense amplifying means in response to the second power control signal.
7. The apparatus as recited in claim 1 , further comprising:
at least one cell array for outputting a stored data to one of the bit line and the bit line bar in response to inputted address and command; and
at least one reference cell array for outputting a reference signal to the other of the bit line and the bit line bar.
8. The apparatus as recited in claim 7 , wherein one cell array is respectively coupled to the sense amplifying means through a plurality of bit lines and the other cell array is coupled to the sense amplifying means through a plurality of bit line bars.
9. The apparatus as recited in claim 7 , wherein one cell array is coupled to the sense amplifying means through a plurality of bit lines and a plurality of bit line bars and the other cell array is not coupled to the sense amplifying means.
10. The apparatus as recited in claim 7 , further comprising a first connection block located between the precharge means and the sense amplifying means for delivering a data loaded in the bit line or the bit line bar into the sense amplifying means and preventing the low voltage from delivering into the bit line and the bit line bar respectively coupled to the cell array.
11. The apparatus as recited in claim 10 , wherein the precharge means includes:
a first MOS transistor for receiving a precharge signal and supplying the ground to the bit line as the precharge voltage in response to the precharge signal; and
a second MOS transistor for receiving the precharge signal and supplying the ground to the bit line bar as the precharge voltage in response to the precharge signal.
12. The apparatus as recited in claim 11 , wherein the first connection block includes:
a first transistor for delivering a data loaded in the bit line into the sense amplifying means and preventing the low voltage from delivering into the bit line in response to a bit line control signal; and
a second transistor for delivering a data loaded in the bit line bar into the sense amplifying means and preventing the low voltage from delivering into the bit line bar in response to the bit line control signal.
13. The apparatus as recited in claim 12 , wherein the sense amplifying means includes:
a first PMOS transistor having a gate, a drain and a source, the gate coupled to the bit line bar, the source for receiving one of the core voltage and the high voltage and the drain coupled to the bit line;
a second PMOS transistor having a gate, a drain and a source, the gate coupled to the bit line, the source for receiving one of the core voltage and the high voltage and the drain coupled to the bit line bar;
a first NMOS transistor having a gate, a drain and a source, the gate coupled to the bit line bar, the source for receiving the ground and the drain coupled to the bit line; and
a second NMOS transistor having a gate, a drain and a source, the gate coupled to the bit line, the source for receiving the ground and the drain coupled to the bit line bar.
14. The apparatus as recited in claim 1 , further comprising a data output means for delivering the data amplified by the sense amplifying means into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into the sense amplifying means.
15. The apparatus as recited in claim 14 , wherein the data output means includes:
a first MOS transistor coupled between the bit line and the data line for delivering a data loaded in the bit line into the data line; and
a second MOS transistor coupled between the bit line bar and the data line bar for delivering a data loaded in the bit line bar into the data line bar.
16. A method for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar in the semiconductor memory device, comprising the steps of:
a) precharging the bit line and the bit line bar as a ground; and
b) sensing and amplifying the data by using a low voltage having a lower voltage level than the ground and a high voltage having a higher voltage level than a supply voltage.
17. The method as recited in claim 16 , wherein the supply voltage and the ground are inputted outside of the semiconductor memory device.
18. The method as recited in claim 17 , further comprising the step of receiving the supply voltage and the ground to thereby generate the low voltage and the high voltage.
19. The method as recited in claim 16 , further comprising the steps of:
c) outputting a stored data to one of the bit line and the bit line bar in response to an inputted address and command; and
d) outputting a reference signal to the other of the bit line and the bit line bar.
20. The method as recited in claim 19 , further comprising the step of e) preventing the low voltage from being delivered into the bit line and the bit line bar respectively coupled to the cell array.
21. The method as recited in claim 20 , wherein the sensing and amplifying includes the steps of:
b 1 ) supplying one of the low voltage and the ground to a sense amplifier in response to a first power control signal and a second power control signal; and
b 2 ) supplying one of the high voltage and the ground to the sense amplifier in response to a third power control signal and the second power control signal.
22. The method as recited in claim 16 , further comprising the step of f) delivering the data amplified by the sense amplifier into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into the sense amplifier.
23. A semiconductor memory device, comprising:
a first cell array having a plurality of unit cells each for storing a data and outputting the data to one of a bit line and a bit line bar in response to an inputted address and command;
a precharge means for precharging the bit line and the bit line bar as a ground; and
a sense amplifying means for sensing and amplifying the data by using a low voltage having a lower voltage level than the ground and a high voltage having a higher voltage level than the core voltage.
24. The semiconductor memory device as recited in claim 23 , wherein the supply voltage and the ground are inputted outside of the semiconductor memory device.
25. The semiconductor memory device as recited in claim 24 , further comprising an internal voltage generator for receiving the supply voltage and the ground to thereby generate the low voltage and the high voltage.
26. The semiconductor memory device as recited in claim 25 , further comprising:
a first voltage supplying block for supplying one of the low voltage and the ground to the sense amplifying means in response to a first power control signal and a second power control signal; and
a second voltage supplying block for supplying one of the high voltage and the ground to the sense amplifying means in response to a third power control signal and the second power control signal.
27. The semiconductor memory device as recited in claim 25 , wherein the first voltage supplying block includes:
a first MOS transistor for outputting the high voltage to the sense amplifying means in response to the first power control signal; and
a second MOS transistor for outputting the ground to the sense amplifying means in response to the second power control signal.
28. The semiconductor memory device as recited in claim 27 , wherein the second voltage supplying block includes:
a third MOS transistor for outputting the low voltage to the sense amplifying means in response to the third power control signal; and
a fourth MOS transistor for outputting the ground to the sense amplifying means in response to the second power control signal.
29. The semiconductor memory device as recited in claim 23 , further comprising a reference cell array for outputting a reference signal to the other of the bit line and the bit line bar.
30. The semiconductor memory device as recited in claim 29 , wherein one cell array is respectively coupled to the sense amplifying means through a plurality of bit lines and the other cell array is coupled to the sense amplifying means through a plurality of bit line bars.
31. The semiconductor memory device as recited in claim 29 , wherein one cell array is coupled to the sense amplifying means through a plurality of bit lines and a plurality of bit line bars and the other cell array is not coupled to the sense amplifying means.
32. The semiconductor memory device as recited in claim 29 , further comprising a connection control block located between the precharge means and the sense amplifying means for delivering a data loaded in the bit line or the bit line bar into the sense amplifying means and preventing the low voltage from delivering into the bit line and the bit line bar respectively coupled to the cell array.
33. The semiconductor memory device as recited in claim 32 , wherein the precharge means includes:
a first MOS transistor for receiving a precharge signal and supplying the ground to the bit line as the precharge voltage in response to the precharge signal; and
a second MOS transistor for receiving the precharge signal and supplying the ground to the bit line bar as the precharge voltage in response to the precharge signal.
34. The semiconductor memory device as recited in claim 33 , wherein the connection control block includes:
a first transistor for delivering a data loaded in the bit line into the sense amplifying means and preventing the low voltage from delivering into the bit line in response to a bit line control signal; and
a second transistor for delivering a data loaded in the bit line bar into the sense amplifying means and preventing the low voltage from delivering into the bit line bar in response to the bit line control signal.
35. The semiconductor memory device as recited in claim 34 , wherein the sense amplifying means includes:
a first PMOS transistor having a gate, a drain and a source, the gate coupled to the bit line bar, the source for receiving one of the core voltage and the high voltage and the drain coupled to the bit line;
a second PMOS transistor having a gate, a drain and a source, the gate coupled to the bit line, the source for receiving one of the core voltage and the high voltage and the drain coupled to the bit line bar;
a first NMOS transistor having a gate, a drain and a source, the gate coupled to the bit line bar, the source for receiving the ground and the drain coupled to the bit line; and
a second NMOS transistor having a gate, a drain and a source, the gate coupled to the bit line, the source for receiving the ground and the drain coupled to the bit line bar.
36. The semiconductor memory device as recited in claim 23 , further comprising a data output means for delivering the data amplified by the sense amplifying means into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into the sense amplifying means.
37. The semiconductor memory device as recited in claim 36 , wherein the data output means includes:
a first MOS transistor coupled between the bit line and the data line for delivering a data loaded in the bit line into the data line; and
a second MOS transistor coupled between the bit line bar and the data line bar for delivering a data loaded in the bit line bar into the data line bar.
38. The semiconductor memory device as recited in claim 23 , further comprising:
a second cell array having a plurality of unit cells each for storing a data and outputting the data to one of a bit line and a bit line bar in response to the inputted address and command;
a first array selection block for connecting or disconnecting the first cell array to the sense amplifying means in response to a first connection signal; and
a second array selection block for connecting or disconnecting the second cell array to the sense amplifying means in response to a second connection signal.
39. The semiconductor memory device as recited in claim 38 , wherein the first and the second array selection signals based on the inputted address and command are activated during a precharging operation.
40. A method for operating a semiconductor memory device, comprising the steps of:
a) storing a data in a first cell array and outputting the data to one of a bit line and a bit line bar in response to an inputted address and command;
b) precharging the bit line and the bit line bar at a ground; and
c) sensing and amplifying the data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage.
41. The method as recited in claim 40 , wherein the supply voltage and the ground are inputted outside of the semiconductor memory device.
42. The method as recited in claim 40 , further comprising the step of receiving a supply voltage inputted to the semiconductor memory device to thereby generate the core voltage and the high voltage.
43. The method as recited in claim 40 , further comprising the step of d) outputting a reference signal outputted from a reference cell to the other of the bit line and the bit line bar.
44. The method as recited in claim 43 , further comprising the step of e) delivering a data or the reference signal respectively loaded in the bit line and the bit line bar into a sense amplifier and preventing the low voltage from delivering into the bit line and the bit line bar respectively coupled to the cell array.
45. The method as recited in claim 44 , wherein the precharging includes the steps of:
b1) supplying one of the low voltage and the ground to the sense amplifying means in response to a first power control signal and a second power control signal; and
b2) supplying one of the high voltage and the ground to the sense amplifying means in response to a third power control signal and the second power control signal.
46. The method as recited in claim 40 , further comprising the step of f) delivering the amplified data into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into a sense amplifier.
47. The method as recited in claim 40 , further comprising the steps of:
g) connecting or disconnecting the first cell array to a sense amplifier in response to a first connection signal; and
h) connecting or disconnecting a second cell array to the sense amplifying means in response to a second connection signal.
48. The method as recited in claim 40 , further comprising the steps of i) restoring the data in the original cell array and outputting the data to one of a bit line and a bit line bar or storing an inputted data through a data line and the data line bar into a cell array in response to the inputted address and command.
49. The method as recited in claim 48 , wherein the first and the second connection signals based on the inputted address and command are activated during a precharging operation.
50. A semiconductor memory device, comprising:
a first cell array having a plurality of unit cells each for storing a data and outputting the data to one of a bit line and a bit line bar in response to an inputted address and command;
a first precharge block coupled to the first cell array for precharging the bit line or the bit line bar of the first cell array by using a ground;
a second cell array having a plurality of unit cells each for storing a data and outputting the data to one of a bit line and a bit line bar in response to the inputted address and command;
a second precharge block coupled to the second cell array for precharging the bit line or the bit line bar of the first cell array by using a ground;
a sense amplifying block for sensing and amplifying the data outputted from one of the first and the second cell arrays by using a high voltage and a low voltage;
a first connection control block located between the sense amplifying block and the first precharge block for connecting or disconnecting the sense amplifying block to the first precharge block; and
a second connection control block located between the sense amplifying block and the first precharge block for connecting or disconnecting the sense amplifying block to the second precharge block.
51. The semiconductor memory device as recited in claim 50 , wherein the low voltage is lower than the ground and the high voltage is higher than a supply voltage inputted from an external circuit.
52. The semiconductor memory device as recited in claim 51 , further comprising:
a first reference cell block for outputting a first reference signal to the sense amplifying block when the first cell array outputs the data; and
a second reference cell block for outputting a second reference signal to the sense amplifying block when the second cell array outputs the data.
53. The semiconductor memory device as recited in claim 52 , further comprising:
a first reference cell block for outputting a first reference signal to the sense amplifying block when the second cell array outputs the data; and
a second reference cell block for outputting a second reference signal to the sense amplifying block when the first cell array outputs the data.