Method for fabricating semiconductor device
View Patent ↗The present invention relates to a method for fabricating a semiconductor device capable of preventing bridge formation caused by damages to a capacitor oxide structure including a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer during a wet cleaning process. The method includes the steps of: forming a PSG layer on a substrate; forming a capping layer on the PSG layer; forming a TEOS layer on the capping layer; selectively etching the TEOS layer, the capping layer and the PSG layer to form a plurality of openings exposing predetermined portions of the substrate; cleaning the openings; forming a conductive layer on the openings; and removing the conductive layer until the TEOS layer is exposed, so that the conductive layer is isolated for each opening.
1. A method for fabricating a semiconductor device, comprising the steps of:
forming a phosphosilicate glass (PSG) layer over a substrate where elements are already formed;
forming a capping layer on the PSG layer;
forming a tetraethylorthosilicate (TEOS) layer on the capping layer;
selectively etching the TEOS layer, the capping layer and the PSG layer to form a plurality of openings exposing predetermined portions of the substrate;
cleaning the openings;
forming a conductive layer on the openings; and
removing the conductive layer until the TEOS layer is exposed, so that the conductive layer is isolated for each opening, wherein the capping layer is formed to prevent phosphorus from diffusing out from the PSG layer to the TEOS layer due to a difference in a phosphorus concentration gradient.
2. The method as recited in claim 1 , wherein the capping layer has a thickness that is approximately 1/19 to approximately 1/9 of that of the PSG layer.
3. The method as recited in claim 1 , wherein the capping layer has a thickness ranging from approximately 100 Å to approximately 500 Å.
4. The method as recited in claim 2 , wherein the capping layer has a thickness ranging from approximately 100 Å to approximately 500 Å.
5. The method as recited in claim 1 , wherein the capping layer is made of a material selected from a group consisting of borophosphosilicate glass (BPSG), undoped silicate glass (USG) and PSG containing phosphorus of which concentration ranges from approximately 1% by volume to approximately 11% by volume.
6. The method as recited in claim 1 , wherein the capping layer is made of a material selected from a group consisting of BPSG, USG and PSG containing phosphorus of which concentration ranges from approximately 1% by volume to approximately 11% by volume.
7. The method as recited in claim 1 , wherein the TEOS layer is formed by employing a plasma enhanced chemical vapor deposition (PECVD) method.
8. The method as recited in claim 1 , wherein a plurality of isolated storage node contact plugs is further formed between the substrate and the PSG layer.
9. The method as recited in claim 8 , wherein the capping layer has a thickness that is approximately 1/9 to approximately 1/9 of that of the PSG layer.
10. The method as recited in claim 8 , wherein the capping layer has a thickness ranging from approximately 100 Å to approximately 500 Å.
11. The method as recited in claim 9 , wherein the capping layer has a thickness ranging from approximately 100 Å to approximately 500 Å.
12. The method as recited in claim 8 , wherein the capping layer is made of a material selected from a group consisting of BPSG, USG and PSG containing phosphorus of which concentration ranges from approximately 1% by volume to approximately 11% by volume.
13. The method as recited in claim 9 , wherein the capping layer is made of a material selected from a group consisting of BPSG, USG and PSG containing phosphorus of which concentration ranges from approximately 1% by volume to approximately 11% by volume.
14. The method as recited in claim 8 , wherein the TEOS layer is formed by employing a PECVD method.