Granted Patent B2

US 7,154,808 · App. 11/125,380 · Granted Dec 26, 2006

Abstract

Claims (43)

1. A semiconductor memory device comprising: a plurality of cell blocks; block controllers for activating or precharging word lines of each of the cell blocks according to an external active command and a precharge command;

a sense amplifier for sensing a fine voltage shared by bit lines and complementary bit lines of the cell blocks;

sense amplifier controllers for activating or precharging the sense amplifier according to the external active command and the precharge command, and outputting a bit line isolation signal that controls the connection between the sense amplifier and the cell block;

a block address decoder for decoding external block addresses in normal mode to output a block select signal for selecting one cell block, and outputting a block select signal for selecting even or odd cell blocks according to one of the external block addresses in test mode; and

a control block for outputting a bit line isolation control signal for controlling the bit line isolation signal and a sense amplifier enable signal according to a test mode signal, a bank active signal and a sense enable start signal.

2. The semiconductor memory device as claimed in claim 1 , wherein the control block enters a normal mode if the test mode signal is a LOW level, thus keeping the bit line isolation signal at a HIGH level, but enters a test mode if the test mode signal is a HIGH level, thus controlling the bit line isolation signal and the sense amplifier enable signal according to the bank active signal and the sense enable start signal.

3. The semiconductor memory device as claimed in claim 1 , wherein the control block comprises:

a first inverter for inverting the test mode signal;

a second inverter for inverting an output of the first inverter;

a third inverter for inverting the sense enable start signal;

a first NOR gate for combining first and second bank active signals;

a second NOR gate for combining third and fourth bank active signals;

a latch for generating a logic signal according to an output of the second inverter, an output of the third inverter, an output of the first NOR gate and an output of the second NOR gate, and latching the logic signal;

a fourth inverter for inverting an output of the latch;

a fifth inverter for inverting the output of the fourth inverter and generating the bit line isolation signal;

a NAND gate for inverting the sense enable start signal according to the output of the latch; and

odd-numbered inverters for inverting an output of the NAND gate.

4. The semiconductor memory device as claimed in claim 1 , wherein the sense amplifier controllers comprise a bit line isolation signal control circuit for generating the bit line isolation signal according to the bit line isolation control signal and the block select signal.

5. The semiconductor memory device as claimed in claim 4 , wherein the bit line isolation signal control circuit comprises:

an inverter for inverting the bit line isolation control signal;

a NAND gate for receiving an output of the inverter and the block select signal;

a level decision circuit for changing an electric potential of a first node to a ground level or a VPP level according to an output of the NAND gate; and

an output circuit for generating a bit line isolation signal of a HIGH level or an isolation signal of a LOW level according to the electric potential of the first node.

6. The semiconductor memory device as claimed in claim 5 , wherein the level decision circuit comprises:

a first NMOS transistor connected between the output of the NAND gate and a second node and having a gate connected to a power supply terminal;

a first PMOS transistor connected between the second node and a VPP power supply terminal and having a gate connected to the first node;

a second PMOS transistor connected between the VPP power supply terminal and the first node and having a gate connected to the second node; and

a second NMOS transistor connected between the first node and a ground terminal and having a gate connected to the output of the NAND gate.

7. The semiconductor memory device as claimed in claim 5 , wherein the output circuit comprises:

a pull-up transistor connected between a VPP power supply terminal and an output terminal, the pull-up transistor being turned on according to the electric potential of the first node; and

a pull-down transistor connected between the output terminal and a ground terminal, the pull-down transistor being turned on according to the electric potential of the first node.

8. The semiconductor memory device as claimed in claim 1 , wherein the block address decoder comprises:

a decoder for decoding block select addresses;

an output unit for outputting a plurality of block select signals according to an output of the decoder; and

a controller for blocking the decoding operation of the decoder according to a given one of the block addresses and a test mode signal, and activating the block select signals by classifying the block select signals into an even number and an odd number.

9. The semiconductor memory device as claimed in claim 8 , wherein the decoder comprises:

first to third inverters for inverting first to third block select addresses, respectively; and

a group of first NAND gates for combining the first to third block select addresses according to an output of the controller, thus outputting decoding signals.

10. The semiconductor memory device as claimed in claim 9 , wherein the output unit comprises a group of second NAND gates for outputting the decoding signals by classifying the decoding signals as an even-numbered signal or an odd-numbered signal according to the output of the controller.

11. The semiconductor memory device as claimed in claim 8 , wherein the controller comprises:

a first NAND gate for combining one of the block select addresses and a test mode signal;

an inverter for inverting the test mode signal and blocking the decoding operation of the decoder according to the inverted signal; and

a second NAND gate for controlling the output unit according to an output of the first NAND gate and the test mode signal.

Assignments (12)