Method for manufacturing semiconductor device
View Patent ↗Disclosed is a method for manufacturing a semiconductor device. According to such a method, in forming a MOSFET to which a double spacer structure is applied, a first spacer of an oxide film is formed after only an upper gate conductive layer is primarily patterned, and then a second spacer of a nitride film is formed after a lower gate conductive layer is etched, so that impurities cannot be diffused up to into the semiconductor substrate through PLDs existing within the oxide film because the first spacer of the oxide film does not come in contact with a semiconductor substrate. Consequently, the gate hump phenomenon is prevented, as a result of which process yield and operation reliability of the device can be improved.
1. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a gate oxide film on a semiconductor substrate;
successively depositing a first gate conductive layer, a second gate conductive layer and a hard mask layer on the gate oxide film;
etching the second gate conductive layer and the hard mask layer over the whole thicknesses thereof and etching the first gate conductive layer over a partial thickness thereof to form first and second gate conducive layer patterns and a hard mask layer pattern, wherein a portion of the unetched first gate conductive layer is exposed;
forming a first spacer of an oxide film on sidewalls of the etched first gate conductive layer, the second gate conductive layer patterns and the hard mask layer pattern, wherein a portion of the unetched first gate conductive layer is covered by the first spacer;
etching a remaining portion of the first gate conductive layer not covered by the first spacer, such that a gate electrode consisting of the first and second gate conductive layer patterns is formed, wherein the remaining portion inclines downwardly; and
forming a second spacer of a nitride film on sidewalls of the first spacer and the first gate conductive layer pattern.
2. The method as claimed in claim 1 , wherein when etching the first gate conductive layer over a partial thickness thereof, 20 to 80 % of a thickness of the first gate conductive layer is etched.
3. The method as claimed in claim 1 , wherein the first spacer is formed of any one selected from the group consisting of a low pressure tetra ethyl ortho silicate (LPTEOS) or a high temperature oxide (HTO) provided by a low pressure chemical vapor deposition (LPCVD) process and an oxide film provided by an atomic layer deposition (ALD) process.
4. The method as claimed in claim 1 , wherein LDD ion implantation is performed after the formation of the gate electrode and before the formation of the second spacer.