Semiconductor device and method for fabricating the same
View Patent ↗A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.
1. A method for forming a semiconductor device, comprising:
forming an insulation layer in a capacitor region and a metal interconnection region on a substrate;
forming a first trench in the insulation layer of the capacitor region and the metal interconnection region;
forming a first barrier metal and a first metal interconnection inside the first trench;
forming a second trench by selectively etching the insulation layer in the capacitor region around the first barrier metal;
forming a third trench in the first barrier metal by selectively etching the first metal interconnection in the capacitor region;
forming a capacitor in the second and third trenches; and
forming a second metal interconnection over the first metal interconnection,
wherein the capacitor and the first metal interconnection are formed in a substantially equivalent vertical plane of the semiconductor device.
2. The method as recited in claim 1 , wherein the first metal interconnection includes copper.
3. The method as recited in claim 1 , wherein the capacitor includes first and second electrodes formed of a metal selected from a group of Pt, Ru, Ir and W.
4. The method as recited in claim 1 , wherein the capacitor includes a dielectric layer is of an oxide selected from a group of Ta oxide, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide, and a combination thereof.
5. A method for fabricating a semiconductor device, comprising:
forming a first insulation layer in a capacitor region and a metal interconnection region on a substrate formed with a lower conductive layer;
forming a second insulation layer on the first insulation layer;
forming an interconnection trench in the metal interconnection region and a first trench in the capacitor region by selectively etching the second insulation layer;
forming a via hole connected to the lower conductive layer by selectively etching the first insulation layer;
forming a copper interconnection, a first copper interconnection and a via contact plug by forming a first copper layer in the interconnection trench, the via hole and the first trench;
forming a second trench by selectively etching the second insulation layer of the capacitor region;
forming a capacitor in the second trench; and
forming a barrier layer on the capacitor and a second copper layer on the barrier layer.
6. The method as recited in claim 5 , further comprising forming an etching blocking layer between the first insulation layer and the second insulation layer.
7. The method as recited in claim 5 , further comprising forming a hard mask on the second insulation layer.
8. The method as recited in claim 5 , wherein forming the interconnection trench further comprises forming the interconnection trench and the first trench simultaneously prior to forming the via hole.
9. The method as recited in claim 5 , wherein forming the interconnection trench further comprises forming the via hole first by selectively etching the first and second insulation layers, and then forming the interconnection trench and the first trench simultaneously.
10. The method as recited in claim 5 , wherein the first and the second copper layers are formed using a reflow method after disposing copper in a sputtering method, a CVD method or an electroplating method.
11. The method as recited in claim 10 , the electroplating method further comprises, forming a seed layer by method selected from the group consisting of a physical vapor deposition (PVD), a chemical vapor deposition (CVD) and an electroless deposition, or a combination thereof.
12. The method as recited in claim 5 , further including forming a first barrier metal prior to the first copper layer.
13. A method for fabricating a semiconductor device, comprising:
forming an insulation layer in a metal interconnection region and the capacitor region on a substrate formed with a lower conductive layer;
forming an interconnection trench in the metal interconnection region, a first trench in the capacitor region and a via hole by selectively etching the insulation layer;
forming a copper interconnection, a via contact plug and a first copper interconnection by forming a first barrier metal and a first copper layer in the interconnection trench, the via hole and the first trench;
forming a second trench by selectively etching the insulation layer around the first copper interconnection in the capacitor region;
forming a third trench in the first barrier metal by selectively etching the first copper interconnection;
forming a capacitor in the second and the third trenches; and
forming a second copper interconnection by forming a second copper layer on the capacitor.
14. The method as recited in claim 13 , wherein a second barrier metal is formed prior to the formation of the second copper layer.
15. The method as recited in claim 14 , wherein the first and the second barrier metals includes a metal selected from a group of Ta, TaN, TiN, WN, TaC, WC, TiSiN and TaSiN, and a combination thereof.